| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhyay |
Modeling and Designing for Accuracy and Energy Efficiency in Wireless Electroencephalography Systems.  |
JETC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Borislav Alexandrov, Owen Sullivan, Satish Kumar, Saibal Mukhopadhyay |
Prospects of active cooling with integrated super-lattice based thin-film thermoelectric devices for mitigating hotspot challenges in microprocessors. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwanyeob Chae, Saibal Mukhopadhyay |
Tier-adaptive-voltage-scaling (TAVS): A methodology for post-silicon tuning of 3D ICs. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay |
Analysis and Design of Energy and Slew Aware Subthreshold Clock Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf |
Modeling and Analysis of Image Dependence and Its Implications for Energy Savings in Error Tolerant Image Processing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay |
Reconfigurable SRAM Architecture With Spatial Voltage Scaling for Low Power Mobile Multimedia Applications. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay |
A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Se Hun Kim, Saibal Mukhopadhyay, Honggab Kim, Marilyn Wolf |
Low energy process variation tolerant digital image processing system design based on accuracy-energy tradeoffs. |
SiPS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin Zhao, Jeremy R. Tolbert, Chang Liu, Saibal Mukhopadhyay, Sung Kyu Lim |
Variation-aware clock network design methodology for ultra-low voltage (ULV) circuits. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
Self-Repairing SRAM Using On-Chip Detection and Compensation. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Subho Chatterjee, Sayeef Salahuddin, Saibal Mukhopadhyay |
Dual-Source-Line-Bias Scheme to Improve the Read Margin and Sensing Accuracy of STTRAM in Sub-90-nm Nodes. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Jason Schlessman, Hamid Mahmoodi, Marilyn Wolf, Saibal Mukhopadhyay |
Postsilicon Adaptation for Low-Power SRAM under Process Variation. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy R. Tolbert, Pratik Kabali, Simeranjit Brar, Saibal Mukhopadhyay |
A low power system with adaptive data compression for wireless monitoring of physiological signals and its application to wireless electroencephalography. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Saibal Mukhopadhyay |
Signal processing methods and hardware-structure for on-line characterization of thermal gradients in many-core processors. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay |
Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migration. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Subho Chatterjee, Sayeef Salahuddin, Satish Kumar, Saibal Mukhopadhyay |
Analysis of thermal behaviors of spin-torque-transfer RAM: a simulation study. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
MTJ, STTRAM, read disturb, self-heating, sensing accuracy |
| 1 | Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili |
An energy efficient cache design using spin torque transfer (STT) RAM. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
(STT)RAM, memory technologies, cache design |
| 1 | Kwanyeob Chae, Saibal Mukhopadhyay, Chang-Ho Lee, Joy Laskar |
A dynamic timing control technique utilizing time borrowing and clock stretching. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, Saibal Mukhopadhyay |
Design method and test structure to characterize and repair TSV defect induced signal degradation in 3D system. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy R. Tolbert, Saibal Mukhopadhyay |
Accurate buffer modeling with slew propagation in subthreshold circuits. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy R. Tolbert, Xin Zhao, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
| 1 | Se Hun Kim, Saibal Mukhopadhyay, Wayne Wolf |
Experimental analysis of sequence dependence on energy saving for error tolerant image processing. |
ISLPED |
2009 |
DBLP DOI BibTeX RDF |
voltage over-scaling, low power, DCT |
| 1 | Dae Hyun Kim, Saibal Mukhopadhyay, Sung Kyu Lim |
Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
wirelength distribution, rent's rule, 3d ic, tsv, interconnect prediction, through silicon via |
| 1 | Minki Cho, Jason Schlessman, Wayne Wolf, Saibal Mukhopadhyay |
Accuracy-aware SRAM: a reconfigurable low power SRAM architecture for mobile multimedia applications. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay |
A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
A variation-aware preferential design approach for memory based reconfigurable computing. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia |
A circuit-software co-design approach for improving EDP in reconfigurable frameworks. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das |
Yield estimation of SRAM circuits using "Virtual SRAM Fab". |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Sourabh Khire, Saibal Mukhopadhyay |
On improving the algorithmic robustness of a low-power FIR filter. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy |
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Profit Aware Circuit Design Under Process Variations Considering Speed Binning. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Rajiv V. Joshi, Keunwoo Kim, Ching-Te Chuang |
Variability Analysis for sub-100nm PD/SOI Sense-Amplifier. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
PD/SOI, dopant fluctuation, sense amplifier, Variation |
| 1 | Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy |
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Design, yield, failure, SRAM, variation |
| 1 | Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy |
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang |
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia |
Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
STTRAM, emerging memory technologies, nonvolatile FPGA |
| 1 | Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang |
Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy |
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. |
Microelectronics Journal |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang |
Design and analysis of Thin-BOX FD/SOI devices for low-power and stable SRAM in sub-50nm technologies. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
FD/SOI, low-power, stability, SRAM |
| 1 | Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
Process Variations and Process-Tolerant Design. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Qikai Chen, Kaushik Roy |
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance. |
DDECS |
2007 |
DBLP BibTeX RDF |
|
| 1 | Amit Agarwal, Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy, Chris H. Kim |
Leakage Power Analysis and Reduction for Nanoscale Circuits. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
nanoscale circuits, CMOS, technology scaling, leakage power reduction |
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy |
Modeling and Analysis of Leakage Currents in Double-Gate Technologies. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy |
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, Saibal Mukhopadhyay, Keejong Kim, Kaushik Roy |
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
adaptive source biasing, hold failures, low power SRAM |
| 1 | Animesh Datta, Swarup Bhunia, Jung Hwan Choi, Saibal Mukhopadhyay, Kaushik Roy |
Speed binning aware design methodology to improve profit under parameter variations. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
Double-Gate SOI Devices for Low-Power and High-Performance Applications. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy |
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy |
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy |
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy |
Low-power scan design using first-level supply gating. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy |
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy |
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy |
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy |
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
double-gate devices, quantum effect, stacking effect, estimation, SRAM, gate leakage, subthreshold leakage |
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy |
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Mahmoodi-Meimand, Kaushik Roy |
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Nilanjan Banerjee, Kaushik Roy |
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Qikai Chen, Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy |
Process Variation Tolerant Online Current Monitor for Robust Systems. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Animesh Datta, Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy |
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology. |
IOLTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici |
Double-gate SOI devices for low-power and high-performance applications. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy |
A Feasibility Study of Subthreshold SRAM Across Technology Generations. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy |
A circuit-compatible model of ballistic carbon nanotube field-effect transistors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, Kaushik Roy |
Leakage in nano-scale technologies: mechanisms, impact and design considerations. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
process variation, leakage current, circuit design |
| 1 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy |
Modeling and Estimation of Leakage in Sub-90nm Devices. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaushik Roy |
Statistical design and optimization of SRAM cell for yield enhancement. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy |
A Novel Low-Power Scan Design Technique Using Supply Gating. |
ICCD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal, Chris H. Kim, Kaushik Roy |
Gate leakage reduction for scaled devices using transistor stacking. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saibal Mukhopadhyay, Kaushik Roy |
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
band-to-band tunneling, variability, Monte Carlo, threshold voltage, gate leakage, subthreshold leakage |
| 1 | Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy |
A forward body-biased low-leakage SRAM cache: device and architecture considerations. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
forward body-biasing, super high VT, SRAM, leakage power |
| 1 | Saibal Mukhopadhyay, Arijit Raychowdhury, Kaushik Roy |
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
doping profiles, leakage, tunneling, threshold voltage |
| 1 | Arijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy |
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
SPICE |
| 1 | Kaushik Roy, Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand |
Leakage Current in Deep-Submicron CMOS Circuits. |
Journal of Circuits, Systems, and Computers |
2002 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")