Search results for "Said Hamdioui"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen	Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	DfT schemes for resistive open defects in RRAMs.	DATE	2012	DBLP BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories.	JETC	2011	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui, Halil Kukner	Generic, orthogonal and low-cost March Element based memory BIST.	ITC	2011	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	On Defect Oriented Testing for Hybrid CMOS/Memristor Memory.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Said Hamdioui, Mottaqiallah Taouil	Yield Improvement and Test Cost Optimization for 3D Stacked ICs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Said Hamdioui, Venkataraman Krishnaswami, Ijeoma Sandra Irobi, Zaid Al-Ars	A New Test Paradigm for Semiconductor Memories in the Nano-Era.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Claude Thibeault	Testing for Parasitic Memory Effect in SRAMs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui	Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.	European Test Symposium	2011	DBLP DOI BibTeX RDF	3D stacked-IC, memory redundancy, 3D memory, yield enhancement
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.	European Test Symposium	2011	DBLP DOI BibTeX RDF	Parasitic Bit Line coupling, SRAMs, Memory tests
1	Nor Zaidi Haron, Said Hamdioui	Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories.	DATE	2011	DBLP DOI BibTeX RDF
1	Seyab Khan, Nor Zaidi Haron, Said Hamdioui, Francky Catthoor	NBTI Monitoring and Design for Reliability in Nanoscale Circuits.	DFT	2011	DBLP DOI BibTeX RDF
1	Ahmed Awad, Abdallatif S. Abu-Issa, Said Hamdioui	Reducing Test Power for Embedded Memories.	DFT	2011	DBLP DOI BibTeX RDF
1	Nivesh Rai, Hamidreza Hashempour, Yizi Xing, Bram Kruseman, Said Hamdioui	A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices.	DFT	2011	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui	Stacking order impact on overall 3D die-to-wafer Stacked-IC cost.	DDECS	2011	DBLP DOI BibTeX RDF
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell	Influence of parasitic memory effect on single-cell faults in SRAMs.	DDECS	2011	DBLP DOI BibTeX RDF
1	Seyab Khan, Said Hamdioui	Modeling and mitigating NBTI in nanoscale circuits.	IOLTS	2011	DBLP DOI BibTeX RDF
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Detecting memory faults in the presence of bit line coupling in SRAM devices.	ITC	2010	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen	On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.	ITC	2010	DBLP DOI BibTeX RDF
1	Mottaqiallah Taouil, Said Hamdioui, Kees Beenakker, Erik Jan Marinissen	Test Cost Analysis for 3D Die-to-Wafer Stacking.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Sandra Irobi, Zaid Al-Ars, Said Hamdioui	Bit line coupling memory tests for single-cell fails in SRAMs.	VTS	2010	DBLP DOI BibTeX RDF
1	Seyab, Said Hamdioui	NBTI modeling in the framework of temperature variation.	DATE	2010	DBLP BibTeX RDF
1	A. J. van de Goor, Georgi Gaydadjiev, Said Hamdioui	Memory testing with a RISC microcontroller.	DATE	2010	DBLP BibTeX RDF
1	A. J. van de Goor, Christian Jung, Said Hamdioui, Georgi Gaydadjiev	Low-cost, customized and flexible SRAM MBIST engine.	DDECS	2010	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui, Georgi Gaydadjiev	Using a CISC microcontroller to test embedded memories.	DDECS	2010	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor	Advanced embedded memory testing: Reducing the defect per million level at lower test cost.	DDECS	2010	DBLP DOI BibTeX RDF
1	Seyab Khan, Said Hamdioui	Temperature dependence of NBTI induced delay.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis	Instruction-Level Fault Tolerance Configurability.	Signal Processing Systems	2009	DBLP DOI BibTeX RDF	Instruction-level configurability, Fault tolerance, Performance, Reliability, Energy consumption
1	Said Hamdioui	Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui, Georgi Nedeltchev Gaydadjiev, Zaid Al-Ars	New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui	Fault Diagnosis Using Test Primitives in Random Access Memories.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui, Sorin Cotofana	Emerging non-CMOS nanoelectronic devices - What are they?.	NEMS	2009	DBLP DOI BibTeX RDF
1	Nor Zaidi Haron, Said Hamdioui	Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.	DFT	2009	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Stamatis Vassiliadis	Test Set Development for Cache Memory in Modern Microprocessors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georg Mueller	Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.	ITC	2008	DBLP DOI BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, Javier Jiménez, Jose Calero	PPM Reduction on Embedded Memories in System on Chip.	European Test Symposium	2007	DBLP DOI BibTeX RDF	static faults, PPM reduction, memory testing, dynamic faults
1	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Optimizing Test Length for Soft Faults in DRAM Devices.	VTS	2007	DBLP DOI BibTeX RDF	DRAM testing, test length optimization, circuit design, memory layout, delay time, soft faults
1	Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev	Manifestation of Precharge Faults in High Speed DRAM Devices.	DDECS	2007	DBLP BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor	Opens and Delay Faults in CMOS RAM Address Decoders.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	address decoder delay faults, addressing methods, BIST, DFT, Memory testing, open defects
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Sultan M. Al-Harbi	Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor, Georgi Gaydadjiev, Jörg E. Vollrath	DRAM-Specific Space of Memory Tests.	ITC	2006	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor	Space of DRAM fault models and corresponding testing.	DATE	2006	DBLP DOI BibTeX RDF
1	Said Hamdioui, John Eleazar Q. Delos Reyes	New data-background sequences and their industrial evaluation for word-oriented random-access memories.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath	Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	memory testing, DRAMs, defect simulation, analytical evaluation, faulty behavior
1	Zaid Al-Ars, Said Hamdioui, Georg Mueller, A. J. van de Goor	Framework for Fault Analysis and Test Generation in DRAMs.	DATE	2005	DBLP DOI BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Said Hamdioui, Rob Wadsworth, John Delos Reyes, A. J. van de Goor	Memory Fault Modeling Trends: A Case Study.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, data backgrounds
1	A. J. van de Goor, Said Hamdioui, Rob Wadsworth	Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.	ITC	2004	DBLP DOI BibTeX RDF	address directions, peripheral circuit faults, fault coverage, March tests, data-backgrounds
1	Said Hamdioui, John Delos Reyes, Zaid Al-Ars	Evaluation of Intra-Word Faults in Word-Oriented RAMs.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor	Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.	VTS	2004	DBLP DOI BibTeX RDF	bit line coupling, DRAMs, Spice simulation, data backgrounds, faulty behavior
1	Said Hamdioui, Georgi Gaydadjiev, A. J. van de Goor	The State-of-Art and Future Trends in Testing Embedded Memories.	MTDT	2004	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui, Zaid Al-Ars	The Effectiveness of the Scan Test and Its New Variants.	MTDT	2004	DBLP DOI BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	static faults, fault models, fault coverage, memory tests, dynamic faults, fault primitives
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor, Mike Rodgers	March SL: A Test For All Static Linked Memory Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	fault coverage, Memory testing, march tests, functional fault models, linked faults
1	Said Hamdioui, A. J. van de Goor, Mike Rodgers	Detecting Intra-Word Faults in Word-Oriented Memories.	VTS	2003	DBLP DOI BibTeX RDF	Bit-oriented/word-oriented memories, fault models, memory tests, data backgrounds
1	Zaid Al-Ars, Said Hamdioui, A. J. van de Goor	A Fault Primitive Based Analysis of Linked Faults in RAMs.	MTDT	2003	DBLP DOI BibTeX RDF	Memory testing, march tests, functional fault models, linked faults, fault primitives
1	Said Hamdioui, A. J. van de Goor	Efficient Tests for Realistic Faults in Dual-Port SRAMs.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Multiport/single-port memories, weak faults, fault models, fault coverage, march tests
1	Said Hamdioui, A. J. van de Goor	Thorough testing of any multiport memory with linear tests.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Said Hamdioui, Zaid Al-Ars, A. J. van de Goor	Testing Static and Dynamic Faults in Random Access Memories.	VTS	2002	DBLP DOI BibTeX RDF	static faults, fault coverage, memory tests, dynamic faults, fault primitives
1	Said Hamdioui, A. J. van de Goor, Mike Rodgers	March SS: A Test for All Static Simple RAM Faults.	MTDT	2002	DBLP DOI BibTeX RDF	simple/linked faults, fault models, fault coverage, Memory testing, march test
1	Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers	Detecting Unique Faults in Multi-port SRAMs.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor, David Eastwick, Mike Rodgers	Realistic Fault Models and Test Procedures for Multi-Port SRAMs.	MTDT	2001	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor	Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	multi-port memories, single-port memories, address decoder faults, read-only ports, write-only ports, fault models, fault coverage, march tests
1	Said Hamdioui, A. J. van de Goor	An experimental analysis of spot defects in SRAMs: realistic fault models and tests.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	integrated circuit testing, fault models, fault coverage, SRAMs, functional fault models, SRAM chips, spot defects
1	Said Hamdioui, A. J. van de Goor, Mike Rodgers, David Eastwick	March Tests for Realistic Faults in Two-Port Memories.	MTDT	2000	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor	Port interference faults in two-port memories.	ITC	1999	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor	March Tests for Word-Oriented Two-Port Memories.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Said Hamdioui, A. J. van de Goor	Consequences of port restrictions on testing two-port memories.	ITC	1998	DBLP DOI BibTeX RDF	Multi-port memories, single-port memories, memory fault models, weak faults, read-only and write-only ports, fault coverage, march tests, test length
1	Said Hamdioui, A. J. van de Goor	Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	A. J. van de Goor, Said Hamdioui	Fault Models and Tests for Two-Port Memories. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF

Publications of "Said Hamdioui" ( http://dblp.L3S.de/Authors/Said_Hamdioui )