| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Buttrick, Sandip Kundu |
On Testing Prebond Dies with Incomplete Clock Networks in a 3D IC Using DLLs. |
J. Electronic Testing |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Nishant Dhumane, Sandip Kundu |
Critical area driven dummy fill insertion to improve manufacturing yield. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu |
On lithography aware metal-fill insertion. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudarshan Srinivasan, Sandip Kundu |
Functional test pattern generation for maximizing temperature in 3D IC chip stack. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Omer Khan, Sandip Kundu |
Hardware/Software Codesign Architecture for Online Testing in Chip Multiprocessors. |
IEEE Trans. Dependable Sec. Comput. |
2011 |
DBLP DOI BibTeX RDF |
hard error detection, isolation and tolerance, Chip Multiprocessor (CMP), hardware/software codesign |
| 1 | Omer Khan, Sandip Kundu |
Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. |
T. HiPEAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Sandip Kundu |
Model based double patterning lithography (DPL) and simulated annealing (SA). |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudarshan Srinivasan, Kunal P. Ganeshpure, Sandip Kundu |
Maximizing hotspot temperature: Wavelet based modelling of heating and cooling profile of functional workloads. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
On discovery of "missing" physical design rules via diagnosis of soft-faults. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu |
Lithography aware critical area estimation and yield analysis. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavan Kumar, Vinay C. Patil, Sandip Kundu |
Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Buttrick, Sandip Kundu |
Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu |
Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu |
On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. |
ISVLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael A. Kochte, Sandip Kundu, Kohei Miyase, Xiaoqing Wen, Hans-Joachim Wunderlich |
Efficient BDD-based Fault Simulation in Presence of Unknown Values. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Sandip Kundu |
An Online Mechanism to Verify Datapath Execution Using Existing Resources in Chip Multiprocessors. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Israel Koren, Sandip Kundu |
An Architecture to Enable Lifetime Full Chip Testability in Chip Multiprocessors. |
PACT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu, Omer Khan |
Performance Per Watt Benefits of Dynamic Core Morphing in Asymmetric Multicores. |
PACT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sudarshan Srinivasan, Bharath Phanibhushana, Arunkumar Vijayakumar, Sandip Kundu |
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavan Kumar, Harikrishnan Kumarapillai Chandrikakutty, Sandip Kundu |
On improving reliability of delay based Physically Unclonable Functions under temperature variations. |
HOST |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu, Aswin Sreedhar |
Modeling manufacturing process variation for design and test. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Michael Buttrick, Sandip Kundu |
On testing prebond dies with incomplete clock networks in a 3D IC using DLLs. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
On design of test structures for lithographic process corner identification. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
Physically unclonable functions for embeded security based on lithographic variation. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Rance Rodrigues, Israel Koren, Sandip Kundu |
An Architecture to Enable Life Cycle Testing in CMPs. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Sandip Kundu |
On graceful degradation of chip multiprocessors in presence of faults via flexible pooling of critical execution units. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Sandip Kundu |
On graceful degradation of microprocessors in presence of faults via resource banking. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bharath Phanibhushana, Kunal P. Ganeshpure, Sandip Kundu |
Task model for on-chip communication infrastructure design for multicore systems. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Ashesh Rastogi, Wei Chen, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
band-to-band-tunneling leakage, loading effect, Newton-Raphson method, gate leakage, Subthreshold leakage |
| 1 | Omer Khan, Sandip Kundu |
Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
hard-error tolerance, virtualization, Chip multiprocessor (CMP), hardware/software codesign, hypervisor |
| 1 | Kunal P. Ganeshpure, Sandip Kundu |
On ATPG for Multiple Aggressor Crosstalk Faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Debasis Mitra, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sandip Kundu, Ashish Nigam, Sandeep K. Dey |
Test pattern generation for droop faults. |
IET Computers & Digital Techniques |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunbean Yi, Sandip Kundu, Sangwook Cho, Sungju Park |
A Scan Cell Design for Scan-Based Debugging of an SoC With Multiple Clock Domains. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunbean Yi, Sungju Park, Sandip Kundu |
On-Chip Support for NoC-Based SoC Debugging. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Syed M. Alam, Sandip Kundu |
BIST to Detect and Characterize Transient and Parametric Failures. |
IEEE Design & Test of Computers |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu |
Modeling the impact of process variation on resistive bridge defects. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Sandip Kundu, Omer Khan |
Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessor. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shruti Vyas, Aswin Sreedhar, Sandip Kundu |
TURBONFS: turbo nand flash search. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
signature, aliasing, NAND flash, MISR |
| 1 | Omer Khan, Sandip Kundu |
A self-adaptive scheduler for asymmetric multi-cores. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
scheduling, modeling, power |
| 1 | Rance Rodrigues, Sandip Kundu |
A mask double patterning technique using litho simulation by wavelet transform. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
double patterning lithography, edge placement error, polygon stitch, wavelet transform |
| 1 | Omer Khan, Sandip Kundu |
A model to exploit power-performance efficiency in superscalar processors via structure resizing. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
modeling, power |
| 1 | Rance Rodrigues, Sandip Kundu |
Optical Lithography Simulation with Focus Variation using Wavelet Transform. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
Critical Dimensions, Edge Detection Value, Wavelet Transform, Wavelet, Aerial Image |
| 1 | Anup Das, Rance Rodrigues, Israel Koren, Sandip Kundu |
A study on performance benefits of core morphing in an asymmetric multicore processor. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rishad Ahmed Shafik, Bashir M. Al-Hashimi, Sandip Kundu, Alireza Ejlali |
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
An Improved Soft-Error Rate Measurement Technique. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Abhisek Pan, Sandip Kundu |
A study on impact of loading effect on capacitive crosstalk noise. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aarti Choudhary, Sandip Kundu |
A Process Variation Tolerant Self-Compensating Sense Amplifier Design. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kelageri Nagaraj, Sandip Kundu |
Process variation mitigation via post silicon clock tuning. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
post-silicon tuning, performance, process variation |
| 1 | Spandana Remarsu, Sandip Kundu |
On process variation tolerant low cost thermal sensor design in 32nm CMOS technology. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
self compensating comparator, dithering, thermal sensor |
| 1 | Aarti Choudhary, Sandip Kundu |
A process variation tolerant self-compensating FinFET based sense amplifier design. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
sense amplifier, robustness, process -variation, yield, sram, finfet |
| 1 | Kunal P. Ganeshpure, Ilia Polian, Sandip Kundu, Bernd Becker |
Reducing temperature variability by routing heat pipes. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
reliability, physical design, thermal modeling, thermal simulation |
| 1 | Alodeep Sanyal, Abhisek Pan, Sandip Kundu |
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
capacitive cross-coupling, dynamic simulation., static analysis |
| 1 | Kunal P. Ganeshpure, Sandip Kundu |
An ILP Based ATPG Technique for Multiple Aggressor Crosstalk Faults Considering the Effects of Gate Delays. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhisek Pan, Omer Khan, Sandip Kundu |
Improving yield and reliability of chip multiprocessors. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Kelageri Nagaraj, Sandip Kundu |
A study on placement of post silicon clock tuning buffers for mitigating impact of process variation. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
On linewidth-based yield analysis for nanometer lithography. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Omer Khan, Sandip Kundu |
A self-adaptive system architecture to address transistor aging. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Omer Khan, Sandip Kundu |
Hardware/software co-design architecture for thermal management of chip multiprocessors. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Omer Khan, Sandip Kundu |
Predictive Thermal Management for Chip Multiprocessors Using Co-designed Virtual Machines. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
Dynamic Thermal Management (DTM), Virtual Thermal Manager (VTM), Dynamic Voltage and Frequency Scaling (DVFS) |
| 1 | Aswin Sreedhar, Sandip Kundu |
Statistical timing analysis based on simulation of lithographic process. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rance Rodrigues, Aswin Sreedhar, Sandip Kundu |
Optical lithography simulation using wavelet transform. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
Lithography Simulation Basics and a Study on Impact of Lithographic Process Window on Gate and Path Delays. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker |
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashesh Rastogi, Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu |
On Composite Leakage Current Maximization. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Leakage Maximizing Pattern Generation (LMPG), Sub-threshold leakage, Band-To-Band Tunneling (BTBT) leakage, Leakage maximization, Weighted max-satisfiability problem, Branch-and-bound heuristic, Gate leakage |
| 1 | Alodeep Sanyal, Sandip Kundu |
A Built-in Test and Characterization Method for Circuit Marginality Related Failures. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR) |
| 1 | Kelageri Nagaraj, Sandip Kundu |
An Automatic Post Silicon Clock Tuning System for Improving System Performance based on Tester Measurements. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
Statistical Yield Modeling for Sub-wavelength Lithography. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On Common-Mode Skewed-Load and Broadside Tests. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Alodeep Sanyal, Sandip Kundu |
On Modeling and Testing of Lithography Related Open Faults in Nano-CMOS Circuits. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhisek Pan, James W. Tschanz, Sandip Kundu |
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunbean Yi, Sandip Kundu |
Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu |
The Guiding Light for Chip Testing. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Syed M. Alam, Sandip Kundu |
A Built-In Self-Test Scheme for Soft Error Rate Characterization. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Omer Khan, Sandip Kundu |
A framework for predictive dynamic temperature management of microprocessor systems. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Aswin Sreedhar, Sandip Kundu |
Modeling and analysis of non-rectangular transistors caused by lithographic distortions. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker |
Power Droop Testing. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
power droop, signal integrity errors, high-frequency effects, low-frequency effects, ATPG, heuristic method, D-algorithm |
| 1 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
On Accelerating Soft-Error Detection by Targeted Pattern Generation. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunal P. Ganeshpure, Sandip Kundu |
On ATPG for multiple aggressor crosstalk faults in presence of gate delays. |
ITC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashesh Rastogi, Wei Chen, Sandip Kundu |
On Estimating Impact of Loading Effect on Leakage Current in Sub-65nm Scaled CMOS Circuits Based on Newton-Raphson Method. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashesh Rastogi, Wei Chen, Alodeep Sanyal, Sandip Kundu |
An Efficient Technique for Leakage Current Estimation in Sub 65nm Scaled CMOS Circuits Based on Loading Effect. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunal P. Ganeshpure, Sandip Kundu |
Interactive presentation: Automatic test pattern generation for maximal circuit noise in multiple aggressor crosstalk faults. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu |
A Study on Impact of Leakage Current on Dynamic Power. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu |
Accelerating Soft Error Rate Testing Through Pattern Selection. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
soft error rate (SER), simulation, automatic test pattern generation (ATPG), Soft error |
| 1 | Alodeep Sanyal, Sandip Kundu |
On Derating Soft Error Probability Based on Strength Filtering. |
IOLTS |
2007 |
DBLP DOI BibTeX RDF |
soft error rate, logic switching threshold voltage, Soft error, single event upset, single event transient |
| 1 | Aswin Sreedhar, Sandip Kundu |
On modeling impact of sub-wavelength lithography on transistors. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu |
TTTC technical forum honoring Sudhakar M. Reddy. |
IEEE Design & Test of Computers |
2006 |
DBLP DOI BibTeX RDF |
Sudhakar M. Reddy, Moore's law, TTTC, ITC 2005 |
| 1 | Debasis Mitra, Subhasis Bhattacharjee, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Sujit T. Zachariah, Sandip Kundu |
Test Pattern Generation for Power Supply Droop Faults. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu |
A design for failure analysis (DFFA) technique to ensure incorruptible signatures. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu, Ilia Polian |
An Improved Technique for Reducing False Alarms Due to Soft Errors. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kunal P. Ganeshpure, Alodeep Sanyal, Sandip Kundu |
A Pattern Generation Technique for Maximizing Power Supply Currents. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Ilia Polian, Alejandro Czutro, Sandip Kundu, Bernd Becker |
Power Droop Testing. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Sandip Kundu, Sujit T. Zachariah, Yi-Shing Chang, Chandra Tirumurti |
On modeling crosstalk faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker |
Transient fault characterization in dynamic noisy environments. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Becker |
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
Temperature testing, Resistive defects, Early-life failures, Low-voltage testing |
| 1 | Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker |
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
Deep submicron technology modeling, Resistive bridging faults |
| 1 | Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy |
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
output response compression, Built-in self-test, scan design |
| 1 | Sandip Kundu |
Pitfalls of hierarchical fault simulation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu |
On the characterization and efficient computation of hard-to-detect bridging faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Rob Aitken, Stefan Eichenberger, Gary Maier, Sandip Kundu, Hank Walker |
ITC 2003 Roundtable: Design for Manufacturability. |
IEEE Design & Test of Computers |
2004 |
DBLP BibTeX RDF |
|
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