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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 5 keywords
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Results
Found 7 publication records. Showing 7 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan |
Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.  |
Integration  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya |
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. |
Design Autom. for Emb. Sys. |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya |
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. |
SCOPES |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya |
Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya |
Buffer memory optimization for video codec application modeled in Simulink. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
memory size reduction, video codec application, Simulink |
| 1 | Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya |
Functional modeling techniques for efficient SW code generation of video codec applications. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
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| 1 | Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya |
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC |
Displaying result #1 - #7 of 7 (100 per page; Change: )
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