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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 8 occurrences of 7 keywords
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Results
Found 26 publication records. Showing 26 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Koushik Chakraborty, Sanghamitra Roy |
Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Satyajit Desai, Sanghamitra Roy, Koushik Chakraborty |
Process variation aware DRAM design using block based adaptive body biasing algorithm. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Kshitij Bhardwaj, Sanghamitra Roy, Koushik Chakraborty |
Power-Performance Yield optimization for MPSoCs using MILP. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
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| 1 | Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy |
An MILP-based aging-aware routing algorithm for NoCs. |
DATE |
2012 |
DBLP BibTeX RDF |
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| 1 | Sanghamitra Roy, Koushik Chakraborty |
Exploiting dynamic micro-architecture usage in gate sizing. |
Microprocessors and Microsystems - Embedded Hardware Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty |
Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. |
J. Low Power Electronics |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala |
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. |
ACM Trans. Design Autom. Electr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty |
Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yiding Han, Sanghamitra Roy, Koushik Chakraborty |
Optimizing simulated annealing on GPU: A case study with IC floorplanning. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy |
Analysis and mitigation of NBTI aging in register file: An end-to-end approach. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala |
A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Koushik Chakraborty, Sanghamitra Roy |
Topologically homogeneous power-performance heterogeneous multicore systems. |
DATE |
2011 |
DBLP BibTeX RDF |
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| 1 | Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy |
Exploring high throughput computing paradigm for global routing. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Koushik Chakraborty, Sanghamitra Roy |
A Novel Threshold Voltage Assignment for 3D Multicore Designs. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Koushik Chakraborty |
A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Koushik Chakraborty, Sanghamitra Roy |
Rethinking Threshold Voltage Assignment in 3D Multicore Designs. |
VLSI Design |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Koushik Chakraborty |
Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. |
ICCD |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng |
An optimal algorithm for sizing sequential circuits for industrial library based designs. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu |
Numerically Convex Forms and Their Application in Gate Sizing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Charlie Chung-Ping Chen |
SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Sanghamitra Roy, Charlie Chung-Ping Chen |
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sanghamitra Roy, Prith Banerjee |
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic |
| 1 | Sanghamitra Roy, Weijen Chen |
ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. |
ICCAD |
2005 |
DBLP BibTeX RDF |
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| 1 | Sanghamitra Roy, Prithviraj Banerjee |
An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
quantization, quantizer, floating point, fixed point |
| 1 | Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee |
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
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| 1 | Biswajit Sarkar, Sanghamitra Roy, Debranjan Sarkar |
Hierarchical representation of digitized curves through dominant point detection. |
Pattern Recognition Letters |
2003 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #26 of 26 (100 per page; Change: )
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