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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 29 occurrences of 25 keywords
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Results
Found 53 publication records. Showing 53 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
DEFCAM: A design and evaluation framework for defect-tolerant cache memories.  |
TACO  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Jin, Sangyeun Cho |
Macro Data Load: An Efficient Mechanism for Enhancing Loaded Data Reuse. |
IEEE Trans. Computers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
C-AMTE: A location mechanism for flexible cache management in chip multiprocessors. |
J. Parallel Distrib. Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem |
Advanced hashing schemes for packet forwarding using set associative memory architectures. |
J. Parallel Distrib. Comput. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Musfiq Rahman, Bruce R. Childers, Sangyeun Cho |
COMeT: Continuous Online Memory Test. |
PRDC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ju-Young Jung, Sangyeun Cho |
PRISM: Zooming in persistent RAM storage behavior. |
ISPASS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Taecheol Oh, Kiyeon Lee, Sangyeun Cho |
An Analytical Performance Model for Co-management of Last-Level Cache and Bandwidth Sharing. |
MASCOTS |
2011 |
DBLP DOI BibTeX RDF |
simulation, performance modeling, Chip multiprocessor (CMP), resource sharing |
| 1 | Michael Moeng, Sangyeun Cho, Rami G. Melhem |
Scalable Multi-cache Simulation Using GPUs. |
MASCOTS |
2011 |
DBLP DOI BibTeX RDF |
General-Purpose GPU, Simulation, Cache, Parallel Architecture, CUDA |
| 1 | Kiyeon Lee, Sangyeun Cho |
In-N-Out: Reproducing Out-of-Order Superscalar Processor Behavior from Reduced In-Order Traces. |
MASCOTS |
2011 |
DBLP DOI BibTeX RDF |
Superscalar out-of-order processor, performance modeling, trace-driven simulation |
| 1 | Ju-Young Jung, Sangyeun Cho |
Dynamic co-management of persistent RAM main memory and storage resources. |
Conf. Computing Frontiers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Socrates Demetriades, Sangyeun Cho |
BarrierWatch: characterizing multithreaded workloads across and within program-defined epochs. |
Conf. Computing Frontiers |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michel Hanna, Sangyeun Cho, Rami G. Melhem |
A Novel Scalable IPv6 Lookup Scheme Using Compressed Pipelined Tries. |
Networking |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
CloudCache: Expanding and shrinking private caches. |
HPCA |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
Cache equalizer: a placement mechanism for chip multiprocessor distributed shared caches. |
HiPEAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
A Dynamic Pressure-Aware Associative Placement Strategy for Large Scale Chip Multiprocessors. |
Computer Architecture Letters |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Lee, Lei Jin, Kiyeon Lee, Socrates Demetriades, Michael Moeng, Sangyeun Cho |
Two-phase trace-driven simulation (TPTS): a fast multicore processor architecture simulation approach. |
Softw., Pract. Exper. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Rami G. Melhem |
On the Interplay of Parallelization, Program Performance, and Energy Consumption. |
IEEE Trans. Parallel Distrib. Syst. |
2010 |
DBLP DOI BibTeX RDF |
energy-delay product (EDP), Multicore processor, dynamic voltage and frequency scaling (DVFS), Amdahl's law |
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
PERFECTORY: A Fault-Tolerant Directory Memory Architecture. |
IEEE Trans. Computers |
2010 |
DBLP DOI BibTeX RDF |
chip yield, lifetime reliability, Chip multiprocessor, cache coherence |
| 1 | Musfiq Rahman, Bruce R. Childers, Sangyeun Cho |
StealthWorks: Emulating Memory Errors. |
RV |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
An intra-tile cache set balancing scheme. |
PACT |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
StimulusCache: Boosting performance of chip multiprocessors with excess cache. |
HPCA |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Lory Al Moakar |
Augmented FIFO Cache Replacement Policies for Low-Power Embedded Processors. |
Journal of Circuits, Systems, and Computers |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Taecheol Oh, Hyunjin Lee, Kiyeon Lee, Sangyeun Cho |
An Analytical Model to Study Optimal Area Breakdown between Cores and Caches in a Chip Multiprocessor. |
ISVLSI |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kiyeon Lee, Shayne Evans, Sangyeun Cho |
Accurately approximating superscalar processor performance from traces. |
ISPASS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Jin, Sangyeun Cho |
SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors. |
PACT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Hyunjin Lee |
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
memory write performance, phase-change memory |
| 1 | Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem |
Progressive hashing for packet processing using set associative memory. |
ANCS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Michel Hanna, Socrates Demetriades, Sangyeun Cho, Rami G. Melhem |
CHAP: Enabling Efficient Hardware-Based Multiple Hash Schemes for IP Lookup. |
Networking |
2009 |
DBLP DOI BibTeX RDF |
hardware multiple hashing, content-based probing, IP lookup |
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
Dynamic cache clustering for chip multiprocessors. |
ICS |
2009 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture (nuca), chip multiprocessor (cmp) |
| 1 | Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem |
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors. |
HiPEAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Tao Li, Onur Mutlu |
Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems. |
IEEE Micro |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Socrates Demetriades, Shayne Evans, Lei Jin, Hyunjin Lee, Kiyeon Lee, Michael Moeng |
TPTS: A Novel Framework for Very Fast Manycore Processor Architecture Simulation. |
ICPP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Jin, Sangyeun Cho |
Taming Single-Thread Program Performance on Many Distributed On-Chip L2 Caches. |
ICPP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Socrates Demetriades, Michel Hanna, Sangyeun Cho, Rami G. Melhem |
An Efficient Hardware-Based Multi-hash Scheme for High Speed IP Lookup. |
Hot Interconnects |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Rami G. Melhem |
Corollaries to Amdahl's Law for Energy. |
Computer Architecture Letters |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Choongyeun Cho, Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Daihyun Lim, Sangyeun Cho, Robert Trzcinski |
A Data-Driven Statistical Approach to Analyzing Process Variation in 65nm SOI Technology. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
Performance of Graceful Degradation for Cache Faults. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad H. Hammoud, Rami G. Melhem |
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. |
ISPASS |
2007 |
DBLP DOI BibTeX RDF |
high-performance search accelerator, high-performance memory substrate, search-intensive application, content addressable random access memory, search operation, memory hierarchy concept, direct hardware implementation, parallel key matching operation, hash function, memory access, application-specific processor, memory structure, hashing technique |
| 1 | Sangyeun Cho |
I-cache multi-banking and vertical interleaving. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
memory sub-banking, cache memory, power density |
| 1 | Lynn Choi, Yunheung Paek, Sangyeun Cho (eds.) |
Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP BibTeX RDF |
|
| 1 | Sangyeun Cho, Lei Jin, Kiyeon Lee |
Achieving Predictable Performance with On-Chip Shared L2 Caches for Manycore-Based Real-Time Systems. |
RTCSA |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Lee, Sangyeun Cho, Bruce R. Childers |
Exploring the interplay of yield, area, and performance in processor caches. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Lei Jin, Hyunjin Lee, Sangyeun Cho |
A flexible data to L2 cache mapping approach for future multicore processors. |
Memory System Performance and Correctness |
2006 |
DBLP DOI BibTeX RDF |
non-uniform cache architecture (NUCA), page allocation |
| 1 | Lei Jin, Sangyeun Cho |
Reducing cache traffic and energy with macro data load. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
LSQ design, low power, memory hierarchy |
| 1 | Sangyeun Cho, Lei Jin |
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Pen-Chung Yew, Gyungho Lee |
A High-Bandwidth Memory Pipeline for Wide Issue Processors. |
IEEE Trans. Computers |
2001 |
DBLP DOI BibTeX RDF |
Data bandwidth, runtime stack, data stream partitioning, multiported data cache, instruction level parallelism, data locality |
| 1 | Sangyeun Cho, Wooyoung Jung, Yongchun Kim, Seh-Woong Jeong |
A Low-Power Cache Design for CalmRISCTM-Based Systems. |
ICCD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Sangyeun Cho, Jinseok Kong, Gyungho Lee |
Coherence and Replacement Protocol of DICE-A Bus-Based COMA Multiprocessor. |
J. Parallel Distrib. Comput. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Pen-Chung Yew, Gyungho Lee |
Decoupling Local Variable Accesses in a Wide-Issue Superscalar Processor. |
ISCA |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Pen-Chung Yew, Gyungho Lee |
Access Region Locality for High-Bandwidth Processor Memory System Design. (PDF / PS) |
MICRO |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Jenn-Yuan Tsai, Yonghong Song, Bixia Zheng, Stephen J. Schwinn, Xin Wang, Qing Zhao, Zhiyuan Li, David J. Lilja, Pen-Chung Yew |
High-Level Information - An Approach for Integrating Front-End and Back-End Compilers. (PDF / PS) |
ICPP |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangyeun Cho, Gyungho Lee |
Reducing Coherence Overhead in Shared-Bus Multiprocessors. |
Euro-Par, Vol. II |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Gyungho Lee, Bland Quattlebaum, Sangyeun Cho, Larry L. Kinney |
Global Bus Design of a Bus-Based COMA Multiprocessor DICE. (PDF / PS) |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
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