Search results for "Sani R. Nassif"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif	Design-aware lithography.	ISPD	2012	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, David Z. Pan, Sani R. Nassif, Keith A. Bowman	Robust and resilient designs from the bottom-up: Technology, CAD, circuit, and system issues.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	The Impact of Statistical Leakage Models on Design Yield Estimation.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif	Simultaneous Layout Migration and Decomposition for Double Patterning Technology.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif	Hierarchical Multialgorithm Parallel Circuit Simulation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Thomas Fröhnel, Sudesh Saroop, Sani R. Nassif, Kevin J. Nowka	The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky	Coupling timing objectives with optical proximity correction for improved timing yield.	ISQED	2011	DBLP DOI BibTeX RDF
1	Eun Jung Jang, Jaeyong Chung, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham	Post-Silicon Timing Validation Method Using Path Delay Measurements.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif	Electrically-driven retargeting for nanoscale layouts.	CICC	2011	DBLP DOI BibTeX RDF
1	Eun Jung Jang, Anne E. Gattiker, Sani R. Nassif, Jacob A. Abraham	Efficient and product-representative timing model validation.	VTS	2011	DBLP DOI BibTeX RDF
1	Mehrdad Majzoobi, Golsa Ghiaasi, Farinaz Koushanfar, Sani R. Nassif	Ultra-low power current-based PUF.	ISCAS	2011	DBLP DOI BibTeX RDF
1	Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta	A framework for double patterning-enabled design.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Zhuo Li, Raju Balasubramanian, Frank Liu, Sani R. Nassif	2011 TAU power grid simulation contest: Benchmark suite and results.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif	Accelerated statistical simulation via on-demand Hermite spline interpolations.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao	Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Sani R. Nassif	'Tis the gift to be simple.	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF	simulation, modeling, IC design
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Statistical leakage modeling for accurate yield analysis: the CDF matching method and its alternatives.	ISLPED	2010	DBLP DOI BibTeX RDF	sram
1	Jente B. Kuang, Jeremy D. Schaub, Fadi H. Gebara, Dieter F. Wendel, Sudesh Saroop, Tuyet Nguyen, Thomas Fröhnel, Antje Müller, Christopher M. Durham, Rolf Sautter, Bryan Lloyd, Bryan J. Robbins, Juergen Pille, Sani R. Nassif, Kevin J. Nowka	A 32nm 0.5V-supply dual-read 6T SRAM.	CICC	2010	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Kevin J. Nowka	Physical design challenges beyond the 22nm node.	ISPD	2010	DBLP DOI BibTeX RDF	technology, scaling
1	Sani R. Nassif	The light at the end of the CMOS tunnel.	ASAP	2010	DBLP DOI BibTeX RDF
1	Shayak Banerjee, Kanak B. Agarwal, Chin-Ngai Sze, Sani R. Nassif, Michael Orshansky	A methodology for propagating design tolerances to shape tolerances for use in manufacturing.	DATE	2010	DBLP BibTeX RDF
1	Sani R. Nassif, Nikil Mehta, Yu Cao	A resilience roadmap.	DATE	2010	DBLP BibTeX RDF
1	Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif	Template-mask design methodology for double patterning technology.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
1	Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
1	Sherief Reda, Sani R. Nassif	Analyzing the impact of process variations on parametric measurements: Novel models and applications.	DATE	2009	DBLP BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Chad Adams, James Warnock, Sani R. Nassif	An elegant hardware-corroborated statistical repair and test methodology for conquering aging effects.	ICCAD	2009	DBLP BibTeX RDF
1	Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif	Simultaneous layout migration and decomposition for double patterning technology.	ICCAD	2009	DBLP BibTeX RDF
1	Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das	Yield estimation of SRAM circuits using "Virtual SRAM Fab".	ICCAD	2009	DBLP BibTeX RDF
1	Kanak Agarwal, Sani R. Nassif	The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Keunwoo Kim, Richard Williams, Sani R. Nassif	Statistical Evaluation of Split Gate Opportunities for Improved 8T/6T Column-Decoupled SRAM Cell Yield.	ISQED	2008	DBLP DOI BibTeX RDF	decoupled design, 8T, 6T, stacked devices, stability, yield, sram, double gate
1	Rouwaida Kanj, Zhuo Li, Rajiv V. Joshi, Frank Liu, Sani R. Nassif	A Root-Finding Method for Assessing SRAM Stability.	ISQED	2008	DBLP DOI BibTeX RDF	stability, memory, yield, sram, roots
1	Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic	A Design Model for Random Process Variability.	ISQED	2008	DBLP DOI BibTeX RDF	random process variability, current variation, modeling, principal component analysis
1	Sani R. Nassif	Model to Hardware Matching for nm Scale Technologies.	PATMOS	2008	DBLP DOI BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Zhou Li, Jente B. Kuang, Hung C. Ngo, Ying Zhou, Weiping Shi, Sani R. Nassif	SRAM methodology for yield and power efficiency: per-element selectable supplies and memory reconfiguration schemes.	ISLPED	2008	DBLP DOI BibTeX RDF
1	Yun Ye, Frank Liu, Sani R. Nassif, Yu Cao	Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness.	DAC	2008	DBLP DOI BibTeX RDF	atomistic simulations, line-edge roughness, non-rectangular gate, random dopant fluctuations, threshold variation, predictive modeling, SPICE simulation
1	Sani R. Nassif	Power grid analysis benchmarks.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Sani R. Nassif	Technology modeling and characterization beyond the 45nm node.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Rajeshwary Tayade, Sani R. Nassif, Jacob A. Abraham	Analytical model for the impact of multiple input switching noise on timing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif	Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Diana Marculescu, Sani R. Nassif	Design Variability: Challenges and Solutions at Microarchitecture-Architecture Level.	DATE	2008	DBLP DOI BibTeX RDF
1	Xiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif	MAPS: multi-algorithm parallel circuit simulation.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Jaijeet S. Roychowdhury (eds.)	2008 International Conference on Computer-Aided Design (ICCAD'08), November 10-13, 2008, San Jose, CA, USA	ICCAD	2008	DBLP BibTeX RDF
1	Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction	CoRR	2007	DBLP BibTeX RDF
1	Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif	Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs.	ISQED	2007	DBLP DOI BibTeX RDF
1	Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham	Estimating path delay distribution considering coupling noise.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	dynamic delay variation, coupling, crosstalk
1	Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao	Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation.	DAC	2007	DBLP DOI BibTeX RDF
1	Kanak Agarwal, Sani R. Nassif	Characterizing Process Variation in Nanometer CMOS.	DAC	2007	DBLP DOI BibTeX RDF
1	Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan	Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis.	DAC	2007	DBLP DOI BibTeX RDF
1	Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer	High-performance CMOS variability in the 65-nm regime and beyond.	IBM Journal of Research and Development	2006	DBLP DOI BibTeX RDF
1	T. M. Mak, Sani R. Nassif	Guest Editors' Introduction: Process Variation and Stochastic Design and Test.	IEEE Design & Test of Computers	2006	DBLP DOI BibTeX RDF	silicon manufacturing processes, adaptive circuits, process variation, process monitoring, subthreshold leakage
1	Fadi J. Kurdahi, Ahmed M. Eltawil, Young-Hwan Park, Rouwaida Kanj, Sani R. Nassif	System-Level SRAM Yield Enhancement.	ISQED	2006	DBLP DOI BibTeX RDF
1	Anand Ramalingam, David Z. Pan, Frank Liu, Sani R. Nassif	Accurate Thermal Analysis Considering Nonlinear Thermal Conductivity.	ISQED	2006	DBLP DOI BibTeX RDF
1	Praveen Elakkumanan, Jente B. Kuang, Kevin J. Nowka, Ramalingam Sridhar, Rouwaida Kanj, Sani R. Nassif	SRAM Local Bit Line Access Failure Analyses.	ISQED	2006	DBLP DOI BibTeX RDF
1	Sani R. Nassif	Model to hardware matching: for nano-meter scale technologies.	ISLPED	2006	DBLP DOI BibTeX RDF	model to hardware correlation, silicon manufacturing variations, integrated circuit modeling
1	Kanak Agarwal, Sani R. Nassif	Statistical analysis of SRAM cell stability.	DAC	2006	DBLP DOI BibTeX RDF	modeling, reliability, stability, SRAM, noise margin
1	Sani R. Nassif, Vijay Pitchumani, N. Rodriguez, Dennis Sylvester, Clive Bittlestone, Riko Radojcic	Variation-aware analysis: savior of the nanometer era?	DAC	2006	DBLP DOI BibTeX RDF	DFY, variability, yield
1	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
1	Sani R. Nassif, Kanak Agarwal, Emrah Acar	Methods for estimating decoupling capacitance of nonswitching circuit blocks.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Emrah Acar, Kanak Agarwal, Sani R. Nassif	Characterization of total chip leakage using inverse (reciprocal) gamma distribution.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan	An accurate sparse matrix based framework for statistical static timing analysis.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Bin Zhang 0011, Ari Arapostathis, Sani R. Nassif, Michael Orshansky	Analytical modeling of SRAM dynamic stability.	ICCAD	2006	DBLP DOI BibTeX RDF
1	Emrah Acar, Anirudh Devgan, Sani R. Nassif	Leakage and Leakage Sensitivity Computation for Combinational Circuits.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar	Power grid analysis using random walks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar	Early-stage power grid analysis for uncertain working modes.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Zhuo Li	A More Effective CEFF.	ISQED	2005	DBLP DOI BibTeX RDF
1	Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham	Testing and debugging delay faults in dynamic circuits.	ITC	2005	DBLP DOI BibTeX RDF
1	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Charles J. Alpert, Sani R. Nassif	An efficient surface-based low-power buffer insertion algorithm.	ISPD	2005	DBLP DOI BibTeX RDF	low-power design, buffer insertion, physical synthesis
1	Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse	The Titanic: what went wrong!	DAC	2005	DBLP DOI BibTeX RDF
1	Anirudh Devgan, Sani R. Nassif	Power Variability and Its Impact on Design.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Peng Li, Frank Liu, Xin Li, Lawrence T. Pileggi, Sani R. Nassif	Modeling Interconnect Variability Using Efficient Parametric Model Order Reduction.	DATE	2005	DBLP DOI BibTeX RDF
1	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif	Power-aware global signaling strategies.	ISCAS	2005	DBLP DOI BibTeX RDF
1	Hailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif	Benefits and Costs of Power-Gating Technique.	ICCD	2005	DBLP DOI BibTeX RDF
1	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	A methodology for the simultaneous design of supply and signal networks.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Juan Antonio Carballo, Sani R. Nassif	Impact of Design-Manufacturing Interface on SoC Design Methodologies.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Sani R. Nassif	The impact of variability on power.	ISLPED	2004	DBLP DOI BibTeX RDF	power, variability, integrated circuit
1	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
1	Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar	Early-stage power grid analysis for uncertain working modes.	ISPD	2004	DBLP DOI BibTeX RDF	early estimation, supply network, random walk, power grid
1	Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula	Variational delay metrics for interconnect timing analysis.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design
1	Haifeng Qian, Joseph N. Kozhaya, Sani R. Nassif, Sachin S. Sapatnekar	A chip-level electrostatic discharge simulation strategy.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Duane S. Boning, Nagib Hakim	The care and feeding of your statistical static timer.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	Optimal decoupling capacitor sizing and placement for standard-cell layout designs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Sani R. Nassif, Soha Hassoun	Guest Editors' Introduction: On-Chip Power Distribution Networks.	IEEE Design & Test of Computers	2003	DBLP BibTeX RDF
1	Ravishankar Arunachalam, Emrah Acar, Sani R. Nassif	Optimal shielding/spacing metrics for low power design.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
1	Haihua Su, Frank Liu, Anirudh Devgan, Emrah Acar, Sani R. Nassif	Full chip leakage estimation considering power supply and temperature variations.	ISLPED	2003	DBLP DOI BibTeX RDF	supply voltage variation, leakage power, thermal analysis
1	Haifeng Qian, Sani R. Nassif, Sachin S. Sapatnekar	Random walks in a supply network.	DAC	2003	DBLP DOI BibTeX RDF	random walk, power grid
1	Haihua Su, Emrah Acar, Sani R. Nassif	Power grid reduction based on algebraic multigrid principles.	DAC	2003	DBLP DOI BibTeX RDF	AC analysis, transient analysis, algebraic multigrid, power grid noise
1	Joseph N. Kozhaya, Sani R. Nassif, Farid N. Najm	A multigrid-like technique for power grid analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi	Time-Domain Simulation of Variational Interconnect Models. (PDF / PS)	ISQED	2002	DBLP DOI BibTeX RDF	simulation, Interconnect, variational models, reduced order modeling
1	Juan Antonio Carballo, Sani R. Nassif	Impact of Technology in Power-Grid-Induced Noise.	PATMOS	2002	DBLP DOI BibTeX RDF
1	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
1	Sani R. Nassif, Onsi Fakhouri	Technology trends in power-grid-induced noise.	SLIP	2002	DBLP DOI BibTeX RDF	power grid noise
1	Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif	Congestion-driven codesign of power and signal networks.	DAC	2002	DBLP DOI BibTeX RDF	signal routing, wire congestion, codesign, power grid noise
1	Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi	A Linear-Centric Simulation Framework for Parametric Fluctuations.	DATE	2002	DBLP DOI BibTeX RDF
1	Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long	Static timing analysis based circuit-limited-yield estimation.	ISCAS	2002	DBLP DOI BibTeX RDF
1	Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu	Test structures for delay variability.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
1	Anne E. Gattiker, Sani R. Nassif, Rashmi Dinakar, Chris Long	Timing Yield Estimation from Static Timing Analysis.	ISQED	2001	DBLP DOI BibTeX RDF
1	Emrah Acar, Lawrence T. Pileggi, Sani R. Nassif, Ying Liu	Assessment of True Worst Case Circuit Performance Under Interconnect Parameter Variations.	ISQED	2001	DBLP DOI BibTeX RDF
1	Sani R. Nassif	Modeling and forecasting of manufacturing variations (embedded tutorial).	ASP-DAC	2001	DBLP DOI BibTeX RDF

Publications of "Sani R. Nassif" ( http://dblp.L3S.de/Authors/Sani_R._Nassif )