Search results for "Sanjay J. Patel"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Minh N. Do, Quang H. Nguyen, Ha T. Nguyen, Daniel Kubacki, Sanjay J. Patel	Immersive Visual Communication.	IEEE Signal Process. Mag.	2011	DBLP DOI BibTeX RDF
1	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: An Adaptive Hybrid Memory Model for Accelerators.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Daniel R. Johnson, Matthew R. Johnson, John H. Kelm, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Rigel: A 1, 024-Core Single-Chip Accelerator Architecture.	IEEE Micro	2011	DBLP DOI BibTeX RDF	Multiple data-stream architectures (multiprocessors), multiple data processors, single-chip multiprocessors, parallel architectures, multicore, parallel processors, multiple instruction
1	Neal Clayton Crago, Sanjay J. Patel	OUTRIDER: efficient memory latency tolerance with decoupled strands.	ISCA	2011	DBLP DOI BibTeX RDF
1	Neal Clayton Crago, Sanjay J. Patel	Decoupled Architectures as a Low-Complexity Alternative to Out-of-order Execution.	PACT	2011	DBLP DOI BibTeX RDF
1	Hongbo Zhang, Tan Yan, Martin D. F. Wong, Sanjay J. Patel	Accelerating aerial image simulation with GPU.	ICCAD	2011	DBLP DOI BibTeX RDF
1	John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Sanjay J. Patel, Matthew I. Frank	A Task-Centric Memory Model for Scalable Accelerator Architectures.	IEEE Micro	2010	DBLP DOI BibTeX RDF	software coherence, parallel architecture, accelerator, memory model
1	Stephen M. Kofsky, Daniel R. Johnson, John A. Stratton, Wen-mei W. Hwu, Sanjay J. Patel, Steven S. Lumetta	Implementing a GPU Programming Model on a Non-GPU Accelerator Architecture.	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	John H. Kelm, Daniel R. Johnson, William Tuohy, Steven S. Lumetta, Sanjay J. Patel	Cohesion: a hybrid memory model for accelerators.	ISCA	2010	DBLP DOI BibTeX RDF	computer architecture, cache coherence, accelerator
1	Omid Azizi, Aqeel Mahesri, Benjamin C. Lee, Sanjay J. Patel, Mark Horowitz	Energy-performance tradeoffs in processor architecture and circuit design: a marginal cost analysis.	ISCA	2010	DBLP DOI BibTeX RDF	co-optimization, design trade-offs, optimization, energy efficiency, design space exploration, microarchitecture
1	John H. Kelm, Matthew R. Johnson, Steven S. Lumetta, Sanjay J. Patel	WAYPOINT: scaling coherence to thousand-core architectures.	PACT	2010	DBLP DOI BibTeX RDF
1	Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone, Sanjay J. Patel, Wen-mei W. Hwu	An asymmetric distributed shared memory model for heterogeneous parallel systems.	ASPLOS	2010	DBLP DOI BibTeX RDF	asymmetric distributed shared memory, data-centric programming models, heterogeneous systems
1	Shobha Vasudevan, David Sheridan, Sanjay J. Patel, David Tcheng, William Tuohy, Daniel R. Johnson	GoldMine: Automatic assertion generation using data mining and static analysis.	DATE	2010	DBLP BibTeX RDF
1	Omid Azizi, Aqeel Mahesri, John P. Stevenson, Sanjay J. Patel, Mark Horowitz	An integrated framework for joint design space exploration of microarchitecture and circuits.	DATE	2010	DBLP BibTeX RDF
1	Sara S. Baghsorkhi, Matthieu Delahaye, Sanjay J. Patel, William D. Gropp, Wen-mei W. Hwu	An adaptive performance modeling tool for GPU architectures.	PPOPP	2010	DBLP DOI BibTeX RDF	parallel programming, analytical model, performance estimation, gpu
1	Thomas Y. Yeh, Glenn Reinman, Sanjay J. Patel, Petros Faloutsos	Fool me twice: Exploring and exploiting error tolerance in physics-based animation.	ACM Trans. Graph.	2009	DBLP DOI BibTeX RDF
1	Omid Azizi, Aqeel Mahesri, Sanjay J. Patel, Mark Horowitz	Area-efficiency in CMP core design: co-optimization of microarchitecture and physical design.	SIGARCH Computer Architecture News	2009	DBLP DOI BibTeX RDF
1	John H. Kelm, Daniel R. Johnson, Matthew R. Johnson, Neal Clayton Crago, William Tuohy, Aqeel Mahesri, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Rigel: an architecture and scalable programming interface for a 1000-core accelerator.	ISCA	2009	DBLP DOI BibTeX RDF	low-level programming interface, computer architecture, accelerator
1	John H. Kelm, Daniel R. Johnson, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	A Task-Centric Memory Model for Scalable Accelerator Architectures.	PACT	2009	DBLP DOI BibTeX RDF
1	Albert Sidelnik, I-Jui Sung, Wanmin Wu, María Jesús Garzarán, Wen-mei W. Hwu, Klara Nahrstedt, David A. Padua, Sanjay J. Patel	Optimization of tele-immersion codes.	GPGPU	2009	DBLP DOI BibTeX RDF	tele-immersion codes, program optimization
1	Quang H. Nguyen, Minh N. Do, Sanjay J. Patel	Depth image-based rendering with low resolution depth.	ICIP	2009	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Wen-mei W. Hwu	Guest Editors' Introduction: Accelerator Architectures.	IEEE Micro	2008	DBLP DOI BibTeX RDF
1	Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel	Tradeoffs in designing accelerator architectures for visual computing.	MICRO	2008	DBLP DOI BibTeX RDF
1	Aqeel Mahesri, Nicholas J. Wang, Sanjay J. Patel	Hardware support for software controlled multithreading.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Nicholas J. Wang, Aqeel Mahesri, Sanjay J. Patel	Examining ACE analysis reliability estimates using fault-injection.	ISCA	2007	DBLP DOI BibTeX RDF	fault tolerance, microprocessors, soft errors, measurement techniques
1	Thomas Y. Yeh, Petros Faloutsos, Sanjay J. Patel, Glenn Reinman	ParallAX: an architecture for real-time physics.	ISCA	2007	DBLP DOI BibTeX RDF	real-time physics, chip multiprocessor, physics based animation, stream processing, interactive entertainment, application specific processor
1	Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman	The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration.	MICRO	2007	DBLP DOI BibTeX RDF
1	Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel	Implicitly Parallel Programming Models for Thousand-Core Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
1	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom-Based Soft Error Detection in Microprocessors.	IEEE Trans. Dependable Sec. Comput.	2006	DBLP DOI BibTeX RDF	Simulation, fault tolerance, fault injection, redundant design
1	Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Jose (Nacho) Navarro, Wen-mei W. Hwu	Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	cache-miss tolerance, prefetching, out-of-order execution, Runahead execution
1	Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer	An Experimental Study of Soft Errors in Microprocessors.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Soft error sensitivity, Assessment and Protection Techniques, Fault Injection, Soft errors, Microprocessor Architecture
1	Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steven S. Lumetta	Continuous Optimization.	ISCA	2005	DBLP DOI BibTeX RDF
1	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom Based Soft Error Detection in Microprocessors.	DSN	2005	DBLP DOI BibTeX RDF
1	Wen-mei W. Hwu, Sanjay J. Patel	The Future of Computer Architecture Research: An Industrial Perspective.	HPCA	2005	DBLP BibTeX RDF
1	Yale N. Patt, Sanjay J. Patel	Introduction to computing systems - from bits and gates to C and beyond (2. ed.).		2004	RDF
1	Nicholas J. Wang, Justin Quek, Todd M. Rafacz, Sanjay J. Patel	Characterizing the Effects of Transient Faults on a High-Performance Processor Pipeline.	DSN	2004	DBLP DOI BibTeX RDF
1	Todd E. Ehrhart, Sanjay J. Patel	Reducing the Scheduling Critical Cycle Using Wakeup Prediction.	HPCA	2004	DBLP DOI BibTeX RDF
1	Francesco Spadini, Brian Fahs, Sanjay J. Patel, Steven S. Lumetta	Improving Quasi-Dynamic Schedules through Region Slip.	CGO	2003	DBLP DOI BibTeX RDF
1	Nicholas J. Wang, Michael Fertig, Sanjay J. Patel	Y-Branches: When You Come to a Fork in the Road, Take It.	IEEE PACT	2003	DBLP DOI BibTeX RDF
1	Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu	Beating in-order stalls with "flea-flicker" two-pass pipelining.	MICRO	2003	DBLP DOI BibTeX RDF
1	Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta	Dynamic Optimization of Micro-Operations.	HPCA	2003	DBLP DOI BibTeX RDF
1	Steven Lumetta, Sanjay J. Patel	Characterization of essential dynamic instructions.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	dynamic instruction stream, reverse analysis
1	Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta	Instruction fetch deferral using static slack.	MICRO	2002	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Steven Lumetta	rePLay: A Hardware Framework for Dynamic Optimization.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	High-performance microarchitecture, dynamic optimization, trace caches
1	Brian Fahs, Satarupa Bose, Matthew M. Crum, Brian Slechta, Francesco Spadini, Tony Tung, Sanjay J. Patel, Steven S. Lumetta	Performance characterization of a hardware mechanism for dynamic optimization.	MICRO	2001	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Tony Tung, Satarupa Bose, Matthew M. Crum	Increasing the size of atomic instruction blocks using control flow assertions.	MICRO	2000	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt	Evaluation of Design Options for the Trace Cache Fetch Mechanism.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	High bandwidth fetch mechanisms, wide issue machines, speculative execution, instruction cache, trace cache
1	Marius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt	An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.	ISCA	1998	DBLP DOI BibTeX RDF
1	Sanjay J. Patel, Marius Evers, Yale N. Patt	Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.	ISCA	1998	DBLP DOI BibTeX RDF
1	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors.	MICRO	1998	DBLP BibTeX RDF
1	Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark	One Billion Transistors, One Uniprocessor, One Chip.	IEEE Computer	1997	DBLP DOI BibTeX RDF
1	Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt	Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism.	MICRO	1997	DBLP BibTeX RDF	high bandwidth fetch mechanisms, wide issue machines, inactive issue, speculative execution, trace cache, partial matching
1	Dina L. McKinney, Masooma Bhaiwala, Kwong-Tak A. Chui, Christopher L. Houghton, James R. Mullens, Daniel L. Leibholz, Sanjay J. Patel, Delvan A. Ramey, Mark B. Rosenbluth	Digital;s DECchip 21066: The First Cost-focused Alpha AXP Chip	Digital Technical Journal	1994	DBLP BibTeX RDF
1	Dina L. McKinney, Daniel L. Leibholz, Mark B. Rosenbluth, James R. Mullens, Kwong-Tak A. Chui, Masooma Bhaiwala, Sanjay J. Patel, Christopher L. Houghton, Delvan A. Ramey	DECchip 21066: The Alpha AXP Chip for Cost-Focused Systems.	COMPCON	1994	DBLP BibTeX RDF
1	Sanjay J. Patel, Janak H. Patel	Effectiveness of heuristics measures for automatic test pattern generation.	DAC	1986	DBLP DOI BibTeX RDF

Publications of "Sanjay J. Patel" ( http://dblp.L3S.de/Authors/Sanjay_J._Patel )