Search results for "Santanu Chattopadhyay"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	S. Krishna Kumar, Subhadip Kundu, Santanu Chattopadhyay	Customizing completely specified pattern set targeting dynamic and leakage power reduction during testing.	Integration	2012	DBLP DOI BibTeX RDF
1	Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur	A Diagnosability Metric for Test Set Selection Targeting Better Fault Detection.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay	And-or-XOR Network Synthesis with Area-Power Trade-Off.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay	Low power finite state machine synthesis using power-gating.	Integration	2011	DBLP DOI BibTeX RDF
1	Soumya J., Putta Venkatesh, Santanu Chattopadhyay	Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay	Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Santanu Kundu, Santanu Chattopadhyay	Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur	Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	S. Krishna Kumar, S. Kaundinya, Subhadip Kundu, Santanu Chattopadhyay	Customizing pattern set for test power reduction via improved X-identification and reordering.	ISLPED	2010	DBLP DOI BibTeX RDF	don't care bits, runtime leakage power, vector reordering, x-fill, dynamic power
1	S. Krishna Kumar, S. Kaundinya, Santanu Chattopadhyay	Particle Swarm Optimization Based Scheme for Low Power March Sequence Generation for Memory Testing.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Saurabh Chaudhury, J. Srinivasa Rao, Santanu Chattopadhyay	State Assignment and Polarity Selection for Low Dynamic Power and Testable Finite State Machine Synthesis.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Saurabh Chaudhury, Krishna Teja Sistla, Santanu Chattopadhyay	Genetic algorithm-based FSM synthesis with area-power trade-offs.	Integration	2009	DBLP DOI BibTeX RDF
1	Subhadip Kundu, Santanu Chattopadhyay	Efficient Don't Care Filling for Power Reduction during Testing.	ARTCom	2009	DBLP DOI BibTeX RDF
1	Santanu Kundu, Kanchan Manna, Shobhit Gupta, Kundan Kumar, Ritesh Parikh, Santanu Chattopadhyay	A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic.	ARTCom	2009	DBLP DOI BibTeX RDF
1	S. Krishna Kumar, P. Uday Bhaskar, Santanu Chattopadhyay, Pradip Mandal	Circuit Partitioning Using Particle Swarm Optimization for Pseudo-Exhaustive Testing.	ARTCom	2009	DBLP DOI BibTeX RDF
1	Subhadip Kundu, S. Krishna Kumar, Santanu Chattopadhyay	Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Ajit Pal, Santanu Chattopadhyay	Synthesis & Testing for Low Power.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Santanu Kundu, Santanu Chattopadhyay	Network-on-chip architecture design based on mesh-of-tree deterministic routing topology.	IJHPSA	2008	DBLP DOI BibTeX RDF
1	Sambhu Nath Pradhan, M. Tilak Kumar, Santanu Chattopadhyay	Integrated Power-Gating and State Assignment for Low Power FSM Synthesis.	ISVLSI	2008	DBLP DOI BibTeX RDF
1	Santanu Kundu, Santanu Chattopadhyay	Mesh-of-tree deterministic routing for network-on-chip architecture.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	deterministic routing., mesh-of-tree (mot), interconnection networks, system-on-chip (soc), network-on-chip (noc)
1	Tapas K. Maiti, Santanu Chattopadhyay	Don't care filling for power minimization in VLSI circuit testing.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Rafiahamed Shaik, Mrityunjoy Chakraborty, Santanu Chattopadhyay	An efficient finite precision realization of the block adaptive decision feedback equalizer.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Mayur Bubna, Naresh Shenoy, Santanu Chattopadhyay	An efficient greedy approach to PLA folding.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay	Test Scheduling for Core-Based SOCs Using Genetic Algorithm Based Heuristic Approach.	ICIC	2007	DBLP DOI BibTeX RDF	wrapper design, test scheduling, test access mechanism, SOC testing
1	Chandan Giri, Soumojit Sarkar, Santanu Chattopadhyay	A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay	Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling.	ICCTA	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, B. Mallikarjuna Rao, Santanu Chattopadhyay	Test Data Compression by Spilt-VIHC (SVIHC).	ICCTA	2007	DBLP DOI BibTeX RDF
1	Chandan Giri, Santanu Chattopadhyay	Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCs.	ISCAS	2007	DBLP DOI BibTeX RDF
1	Saurabh Chaudhury, Santanu Chattopadhyay, J. Srinivasa Rao	Synthesis of Finite State Machines for Low Power and Testability.	APCCAS	2006	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay	Area Conscious State Assignment with Flip-Flop and Output Polarity Selection for Finite State Machine Synthesis?A Genetic Algorithm Approach.	Comput. J.	2005	DBLP DOI BibTeX RDF
1	Shantanu Gupta, Tarang Vaish, Santanu Chattopadhyay	Flip-flop chaining architecture for power-efficient scan during test application.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, Manas Kumar Dewangan	A Combinational Logic Mapper for Actel's SX/AX Family.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Batsayan Das, Dipankar Sarkar, Santanu Chattopadhyay	Model checking on state transition diagram.	ASP-DAC	2004	DBLP DOI BibTeX RDF	CTL model checking, Finite State Machine (FSM), State Transition Diagram (STD), Kripke structure
1	D. Satyanarayana, Santanu Chattopadhyay, Jakki Sasidhar	Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, Naveen Choudhary	Genetic Algorithm based Approach for Low Power Combinational Circuit Testing.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Rohit Pandey, Santanu Chattopadhyay	Low Power Technology Mapping for LUT based FPGA "A Genetic Algorithm Approach".	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, K. Sudarsana Reddy	Genetic Algorithm based Test Scheduling and Test Access Mechanism Design for System-on-Chips.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay	Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	cellular automata, Test pattern generators, pseudoexhaustive testing
1	Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta	Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Data path architecture, cellular automata, BIST, pseudoexhaustive testing
1	Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta	Theory and application of non-group cellular automata for message authentication.	Journal of Systems Architecture	2001	DBLP DOI BibTeX RDF
1	Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay	A Novel Strategy to Test Core Based Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta	An ASIC for Cellular Automata Based Message Authentication.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Prabir Dasgupta, Santanu Chattopadhyay, Indranil Sengupta	Cellular Automata Based Deterministic Test Sequence Generator for Sequential Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri	Cellular-Automata-Array-Based Diagnosis of Board Level Faults.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	VLSI, Fault diagnosis, cellular automata, error correcting code, multichip module
1	Kolin Paul, A. Roy, Prasanta Kumar Nandi, B. N. Roy, M. Deb Purkayastha, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Theory and Application of Multiple Attractor Cellular Automata for Fault Diagnosis. (PDF / PS)	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, Parimal Pal Chaudhuri	Efficient Signatures with Linear Space Complexity for Detecting Boolean Function Equivalence.	VLSI Design	1998	DBLP BibTeX RDF
1	Santanu Chattopadhyay, Parimal Pal Chaudhuri	Genetic Algorithm Based Approach for Integrated State Assignment and Flipflop Selection in Finite State Machine Synthesis.	VLSI Design	1998	DBLP BibTeX RDF
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	KGPMIN: an efficient multilevel multioutput AND-OR-XOR minimizer.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Santanu Chattopadhyay, Parimal Pal Chaudhuri	Parallel Decoder for Cellular Automata Based Byte Error Correcting Code.	VLSI Design	1997	DBLP DOI BibTeX RDF	byte error correcting code, SbEC/DbED code, DbEC/DbED code, design, cellular automata, cellular automata, Reed-Solomon code, parallel decoder
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Synthesis of Highly Testable Fixed-Polarity AND-XOR Canonical Networks-A Genetic Algorithm-Based Approach.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Reed Muller form, AND-XOR network synthesis, fixed-polarity canonical expansion, genetic algorithm
1	Koppolu Sasidhar, Santanu Chattopadhyay, Parimal Pal Chaudhuri	CAA Decoder for Cellular Automata Based Byte Error Correcting Code.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	cellular automata array (CAA), error vector, error space, Cellular automata, error correcting code
1	S. Nandi, Santanu Chattopadhyay, Parimal Pal Chaudhuri	Programmable cellular automata based testbed for fault diagnosis in VLSI circuits.	VLSI Design	1996	DBLP DOI BibTeX RDF	programmable cellular automata, polynomial algebraic tools, faulty signatures, multiple attractor, fault dictionary size, cascadable structure, VLSI, fault diagnosis, fault diagnosis, logic testing, partitions, cellular automata, integrated circuit testing, automatic testing, VLSI circuits, logic partitioning, signature analyzer
1	Santanu Chattopadhyay, S. Mitra, Parimal Pal Chaudhuri	Cellular automata based architecture of a database query processor.	VLSI Design	1996	DBLP DOI BibTeX RDF	cellular automata based architecture, database query processor, programmable query processor chip, fast database access, multiple attractor cellular automata, class-relation storage, true/false classifier, classification, VLSI, query processing, relational databases, relational database, cellular automata, microprocessor chips, database machines
1	Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri	Board level fault diagnosis using cellular automata array.	VLSI Design	1995	DBLP DOI BibTeX RDF	board level fault diagnosis, cellular automata array, output responses, encoding strategy, byte error correcting code, encoded symbols, decoding structure, VLSI, fault diagnosis, logic testing, cellular automata, error correction codes, VLSI implementation, test vectors
1	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture

Publications of "Santanu Chattopadhyay" ( http://dblp.L3S.de/Authors/Santanu_Chattopadhyay )