Search results for "Saraju P. Mohanty"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Saraju P. Mohanty, Jawar Singh, Elias Kougianos, Dhiraj K. Pradhan	Statistical DOE-ILP based power-performance-process (P3) optimization of nano-CMOS SRAM.	Integration	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos	Ordinary Kriging metamodel-assisted Ant Colony algorithm for fast analog design optimization.	ISQED	2012	DBLP DOI BibTeX RDF
1	Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Saraju P. Mohanty	Low complexity cross parity codes for multiple and random bit error correction.	ISQED	2012	DBLP DOI BibTeX RDF
1	G. K. Reddy, Kapil Jainwal, Jawar Singh, Saraju P. Mohanty	Process variation tolerant 9T SRAM bitcell design.	ISQED	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Oghenekarho Okobiah	Metamodel-assisted ultra-fast memetic optimization of a PLL for WiMax and MMDS applications.	ISQED	2012	DBLP DOI BibTeX RDF
1	Pranav Yeolekar, Rishad A. Shafik, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	STEP: a unified design methodology for secure test and IP core protection.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos, Geng Zheng	Particle swarm optimization over non-polynomial metamodels for fast process variation resilient design of Nano-CMOS PLL.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Geng Zheng, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Verilog-AMS-PAM: verilog-AMS integrated with parasitic-aware metamodels for ultra-fast and layout-accurate mixed-signal design exploration.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast-Accurate Non-Polynomial Metamodeling for Nano-CMOS PLL Design Optimization.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Oleg Garitselov	Kriging-Assisted Ultra-Fast Simulated-Annealing Optimization of a Clamped Bitline Sense Amplifier.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Shibaji Banerjee, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan, Maciej J. Ciesielski	A Variation-Aware Taylor Expansion Diagram-Based Approach for Nano-CMOS Register-Transfer Level Leakage Optimization.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Real-time perceptual watermarking architectures for video broadcasting.	Journal of Systems and Software	2011	DBLP DOI BibTeX RDF
1	Shibaji Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Bhargab B. Bhattacharya, Saraju P. Mohanty	A Routing-Aware ILS Design Technique.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty	BCH code based multiple bit error correction in finite field multiplier circuits.	ISQED	2011	DBLP DOI BibTeX RDF
1	Oleg Garitselov, Saraju P. Mohanty, Elias Kougianos	Fast optimization of nano-CMOS mixed-signal circuits through accurate metamodeling.	ISQED	2011	DBLP DOI BibTeX RDF
1	Oghenekarho Okobiah, Saraju P. Mohanty, Elias Kougianos, Mahesh Poolakkaparambil	Towards robust nano-CMOS sense amplifier design: a dual-threshold versus dual-oxide perspective.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski	Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Garima Thakral, Saraju P. Mohanty, Dhiraj K. Pradhan, Elias Kougianos	DOE-ILP Based Simultaneous Power and Read Stability Optimization in Nano-CMOS SRAM.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Yu-Ting Pai, Li-Te Lee, Shanq-Jang Ruan, Yen-Hsiang Chen, Saraju P. Mohanty, Elias Kougianos	Honeycomb model based skin colour detector for face detection.	IJCAT	2010	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Dhiraj K. Pradhan	ULS: A dual-Vth/high-kappa nano-CMOS universal level shifter for system-level power management.	JETC	2010	DBLP DOI BibTeX RDF
1	Suman Kalyan Mandal, Rabi N. Mahapatra, Praveen Bhojwani, Saraju P. Mohanty	IntellBatt: Toward a Smarter Battery.	IEEE Computer	2010	DBLP DOI BibTeX RDF	IntellBatt, Battery management, Smart battery, Low-power design, Hardware
1	Savita Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Layout-aware Illinois Scan design for high fault coverage coverage.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jawar Singh, Dilip S. Aswar, Saraju P. Mohanty, Dhiraj K. Pradhan	A 2-port 6T SRAM bitcell design with multi-port capabilities at reduced area overhead.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jimson Mathew, Hafizur Rahaman, Abusaleh M. Jabir, Saraju P. Mohanty, Dhiraj K. Pradhan	On the design of different concurrent EDC schemes for S-Box and GF(p).	ISQED	2010	DBLP DOI BibTeX RDF
1	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP.	ISQED	2010	DBLP DOI BibTeX RDF
1	Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir	On the synthesis of attack tolerant cryptographic hardware.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
1	Suman Kalyan Mandal, Ron Denton, Saraju P. Mohanty, Rabi N. Mahapatra	Low power nanoscale buffer management for network on chip routers.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nanoscale technology noc, soc, noc, router, dynamic power management
1	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	nano-CMOS, power, leakage, SRAM, static noise margin
1	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos	A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO.	VLSI Design	2010	DBLP DOI BibTeX RDF
1	Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dhiraj K. Pradhan	A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM.	VLSI Design	2010	DBLP DOI BibTeX RDF	Nanoscale CMOS, SRAM, Power Dissipation, Static Noise Margin
1	Elias Kougianos, Saraju P. Mohanty	Impact of gate-oxide tunneling on mixed-signal design and simulation of a nano-CMOS VCO.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty	A secure digital camera architecture for integrated real-time digital rights management.	Journal of Systems Architecture - Embedded Systems Design	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nasir Memon, Karam S. Chatha	Circuits and systems for real-time security and copyright protection of multimedia.	Computers & Electrical Engineering	2009	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty, Rabi N. Mahapatra	Hardware assisted watermarking for multimedia.	Computers & Electrical Engineering	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments.	ISQED	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Wei Cai, Manish Ratnani	VLSI architectures of perceptual based video watermarking for real-time copyright protection.	ISQED	2009	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Dhruva Ghai, Elias Kougianos, Bharat Joshi	A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems.	ISQED	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos, Priyadarsan Patra	A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS.	ISQED	2009	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dual oxide technology, nano-cmos, performance aware design, vco, process variation, parasitics, power aware design
1	Saraju P. Mohanty	Unified Challenges in Nano-CMOS High-Level Synthesis.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	Single Ended Static Random Access Memory for Low-Vdd, High-Speed Embedded Systems.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew	Single ended 6T SRAM with isolated read-port for low-power embedded systems.	DATE	2009	DBLP BibTeX RDF
1	Saraju P. Mohanty, Bharat K. Bhargava	Invisible watermarking based on creation and robust insertion-extraction of image adaptive watermarks.	TOMCCAP	2008	DBLP DOI BibTeX RDF	invisible watermarking, Watermarking, image, copyright protection, content protection
1	Saraju P. Mohanty, Elias Kougianos, Dhiraj K. Pradhan	Simultaneous scheduling and binding for low gate leakage nano-complementary metaloxide-semiconductor data path circuit behavioural synthesis.	IET Computers & Digital Techniques	2008	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty	ILP Based Gate Leakage Optimization Using DKCMOS Library during RTL Synthesis.	ISQED	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A Dual Oxide CMOS Universal Voltage Converter for Power Management in Multi-VDD SoCs.	ISQED	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	Parasitic Aware Process Variation Tolerant Voltage Controlled Oscillator (VCO) Design.	ISQED	2008	DBLP DOI BibTeX RDF
1	Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos	A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	flash adc, nano-cmos, ti comparator, process variation, analog-to-digital converter, low voltage, high speed
1	Suman Kalyan Mandal, Praveen Bhojwani, Saraju P. Mohanty, Rabi N. Mahapatra	IntellBatt: towards smarter battery design.	DAC	2008	DBLP DOI BibTeX RDF	battery management, intelligent battery scheduling, smart battery
1	Jawar Singh, Jimson Mathew, Saraju P. Mohanty, Dhiraj K. Pradhan	A nano-CMOS process variation induced read failure tolerant SRAM cell.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies.	SoCC	2008	DBLP DOI BibTeX RDF
1	Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty	Failure analysis for ultra low power nano-CMOS SRAM under process variations.	SoCC	2008	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan	VLSI architecture and chip for combined invisible robust and fragile watermarking.	IET Computers & Digital Techniques	2007	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty	Metrics to Quantify Steady and Transient Gate Leakage in Nanoscale Transistors: NMOS vs. PMOS Perspective.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Wentong Li, Saraju P. Mohanty, Krishna M. Kavi	A Page-based Hybrid (Software-Hardware) Dynamic Memory Allocator.	Computer Architecture Letters	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	ILP models for simultaneous energy and transient power minimization during behavioral synthesis.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	average power, cycle difference power, datapath scheduling, dynamic frequency clocking, multicycling, multiple supply voltages, peak power differential, Peak power
1	Cheryl A. Kincaid, Saraju P. Mohanty, Armin R. Mikler, Elias Kougianos, Brandon Parker	A High Performance ASIC for Cellular Automata (CA) Applications.	ICIT	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Anirudha Sahoo (eds.)	9th International Conference in Information Technology, ICIT 2006, Bhubaneswar, Orissa, India, 18-21 December 2006	ICIT	2006	DBLP BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Dual-K Versus Dual-T Technique for Gate Leakage Reduction : A Comparative Perspective.	ISQED	2006	DBLP DOI BibTeX RDF
1	Yue Zhuo, Hao Li, Saraju P. Mohanty	A Congestion Driven Placement Algorithm for FPGA Synthesis.	FPL	2006	DBLP DOI BibTeX RDF
1	Wentong Li, Saraju P. Mohanty, Krishna M. Kavi	A Hardware Assisted High Performance PHK Memory Manager.	ISCA PDCS	2006	DBLP BibTeX RDF
1	Naga M. Kosaraju, Murali R. Varanasi, Saraju P. Mohanty	A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Modeling and Reduction of Gate Leakage during Behavioral Synthesis of NanoCMOS Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos	Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits.	DATE	2006	DBLP DOI BibTeX RDF
1	Elias Kougianos, Saraju P. Mohanty	Effective tunneling capacitance: a new metric to quantify transient gate leakage current.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos, Ramakrishna Velagapudi, Valmiki Mukherjee	Scheduling and binding for low gate leakage nanoCMOS datapath circuit synthesis.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Parthasarathy Guturu, Elias Kougianos, Nishikanta Pati	A Novel Invisible Color Image Watermarking Scheme Using Image Adaptive Watermark Creation and Robust Insertion-Extraction.	ISM	2006	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Elias Kougianos	Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates.	ICCD	2006	DBLP BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan	Energy-efficient datapath scheduling using multiple voltages and dynamic clocking.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	dynamic frequency clocking, low-power datapath synthesis, multiple voltage scheduling, time-constrained scheduling, High-level synthesis, resource-constrained scheduling
1	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa	A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa	A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki Mukherjee, Hao Li	Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan	Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Valmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos	A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits.	ICCD	2005	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan	A framework for energy and transient power reduction during behavioral synthesis.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Renuka Kumara C., Sridhara Nayak	FPGA Based Implementation of an Invisible-Robust Image Watermarking Encoder.	CIT	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa	VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi	ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Peak Power Minimization Through Datapath Scheduling.	ISVLSI	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Simultaneous peak and average power minimization during datapath scheduling for DSP processors.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	average power, datapath scheduling, dynamic frequency clocking, high-level synthesis, peak power, multiple voltages
1	Saraju P. Mohanty, N. Ranganathan	A Framework for Energy and Transient Power Reduction during Behavioral Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan	Energy Efficient Scheduling for Datapath Synthesis.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.	ISCAS	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi	Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.	ICCD	2003	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna	Datapath Scheduling using Dynamic Frequency Clocking.	ISVLSI	2002	DBLP DOI BibTeX RDF
1	Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli	A DCT Domain Visible Watermarking Technique for Images.	IEEE International Conference on Multimedia and Expo (II)	2000	DBLP BibTeX RDF
1	Saraju P. Mohanty, K. R. Ramakrishnan, Mohan S. Kankanhalli	A dual watermarking technique for images.	ACM Multimedia	1999	DBLP DOI BibTeX RDF

Publications of "Saraju P. Mohanty" ( http://dblp.L3S.de/Authors/Saraju_P._Mohanty )