| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Benjamin Gaudette, Vinay Hanumaiah, Sarma B. K. Vrudhula, Marwan Krunz |
Optimal range assignment in solar powered active wireless sensor networks.  |
INFOCOM  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha |
Performance Optimal Online DVFS and Task Migration Techniques for Thermally Constrained Multi-Core Processors. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Tejaswi Gowda, Sarma B. K. Vrudhula, N. Kulkarni, Krzysztof S. Berezowski |
Identification of Threshold Functions and Synthesis of Threshold Networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula |
A new balanced 4-moduli set {2k, 2n - 1, 2n + 1, 2n+1-1} and its reverse converter design for efficient fir filter implementation. |
ACM Great Lakes Symposium on VLSI |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Jared Pager, Reiley Jeyapaul, Mahdi Hamzeh, Sarma B. K. Vrudhula |
Enabling Multithreading on CGRAs. |
ICPP |
2011 |
DBLP DOI BibTeX RDF |
CGRA, processor accelerator, dynamic threading, runtime scheduling, page-based mapping, CGRA mapping technique, low power, multithreading, compiler optimization, scheduling technique |
| 1 | Vinay Hanumaiah, Sarma B. K. Vrudhula |
Reliability-aware thermal management for hard real-time applications on multi-core processors. |
DATE |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Aviral Shrivastava, Deepa Kannan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Reducing Functional Unit Power Consumption and its Variation Using Leakage Sensors. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Frank Liu, Yu Cao |
The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula |
A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. |
ISVLSI |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Fast and Accurate Prediction of the Steady-State Throughput of Multicore Processors Under Thermal Constraints. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang, Sarma B. K. Vrudhula |
Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrudhula, Karam S. Chatha |
Throughput optimal task allocation under thermal constraints for multi-core processors. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
optimal throughput, task allocation, thermal management, multi-core processors, thread migration |
| 1 | Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha |
Performance optimal speed control of multi-core processors under thermal constraints. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Vinay Hanumaiah, Sarma B. K. Vrudhula, Karam S. Chatha |
Maximizing performance of thermally constrained multi-core processors by dynamic voltage and frequency control. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Michael A. Baker, Pravin Dalale, Karam S. Chatha, Sarma B. K. Vrudhula |
A scalable parallel H.264 decoder on the cell broadband engine architecture. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
code overlay, scalable, parallel, video, multicore, H.264, cell broadband engine, MPEG4 |
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Multi-Attribute Optimization with Application to Leakage-Delay Trade-Offs Using Utility Theory. |
J. Low Power Electronics |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula |
A fuel-cell-battery hybrid for portable embedded systems. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Simulation, simulator, hybrid systems, battery, DPM, fuel cell |
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel |
A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Ramamoorthy, Haibo Wang, Sarma B. K. Vrudhula |
A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
low power, memory, circuit design, FIFO |
| 1 | Amit Goel, Sarma B. K. Vrudhula, Feroze Taraporevala, Praveen Ghanta |
A Methodology for Characterization of Large Macro Cells and IP Blocks Considering Process Variations. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Krzysztof S. Berezowski |
Analytical results for design space exploration of multi-core processors employing thread migration. |
ISLPED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Goel, Sarma B. K. Vrudhula |
Statistical waveform and current source based standard cell models for accurate timing analysis. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
statistical waveform models, process variations, timing analysis |
| 1 | Tejaswi Gowda, Sarma B. K. Vrudhula |
Decomposition based approach for synthesis of multi-level threshold logic circuits. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Temperature and Process Variations Aware Power Gating of Functional Units. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Power Reduction of Functional Units Considering Temperature and Process Variations. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Tejaswi Gowda, Samuel Leshner, Sarma B. K. Vrudhula, Seungchan Kim |
Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. |
BIODEVICES |
2008 |
DBLP BibTeX RDF |
|
| 1 | Amit Goel, Sarma B. K. Vrudhula |
Current source based standard cell model for accurate signal integrity and timing analysis. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processors. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Energy optimal speed control of a producer--consumer device pair. |
ACM Trans. Embedded Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
joint optimization, processor, Energy optimization, disk drive, speed control |
| 1 | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang |
Stochastic Power Grid Analysis Considering Process Variations |
CoRR |
2007 |
DBLP BibTeX RDF |
|
| 1 | Krzysztof S. Berezowski, Sarma B. K. Vrudhula |
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. |
Multiple-Valued Logic and Soft Computing |
2007 |
DBLP BibTeX RDF |
|
| 1 | Praveen Ghanta, Sarma B. K. Vrudhula |
Analysis of Power Supply Noise in the Presence of Process Variations. |
IEEE Design & Test of Computers |
2007 |
DBLP DOI BibTeX RDF |
voltage response, verification, computer-aided design, process variations, modeling methodologies, power supply noise |
| 1 | Amit Goel, Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
Computation of Joint Timing Yield of Sequential Networks Considering Process Variations. |
PATMOS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti |
Throughput of multi-core processors under thermal constraints. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
leakage dependence on temperature, throughput, power, speedup, thermal management, multi-core processors |
| 1 | Tejaswi Gowda, Sarma B. K. Vrudhula, Goran Konjevod |
Combinational equivalence checking for threshold logic circuits. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
nano devices, EDA, equivalence checking, threshold logic |
| 1 | Wenping Wang, Shengqi Yang, Sarvesh Bhardwaj, Rakesh Vattikonda, Sarma B. K. Vrudhula, Frank Liu, Yu Cao |
The Impact of NBTI on the Performance of Combinational and Sequential Circuits. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Krzysztof S. Berezowski, Sarma B. K. Vrudhula |
Multiple-Valued Logic Circuits Design Using Negative Differential Resistance Devices. |
ISMVL |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Performance optimal processor throttling under thermal constraints. |
CASES |
2007 |
DBLP DOI BibTeX RDF |
leakage dependence on temperature, power, thermal management, thermal model, throttling |
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
A Fast and Accurate approach for Full Chip Leakage Analysis of Nano-scale circuits considering Intra-die Correlations. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarma B. K. Vrudhula, Sarvesh Bhardwaj |
Tutorial T6: Robust Design of Nanoscale Circuits in the Presence of Process Variations. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula |
Statistical Leakage Minimization of Digital Circuits Using Gate Sizing, Gate Length Biasing, Threshold Voltage Selection. |
J. Low Power Electronics |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula |
Joint Optimization of Transmit Power-Time and Bit Energy Efficiency in CDMA Wireless Sensor Networks. |
IEEE Transactions on Wireless Communications |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarma B. K. Vrudhula, Janet Meiling Wang, Praveen Ghanta |
Hermite Polynomial Based Interconnect Analysis in the Presence of Process Variations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Energy-Optimal Speed Control of a Generic Device. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Praveen Ghanta, Sarma B. K. Vrudhula |
Variational Interconnect Delay Metrics for Statistical Timing Analysis. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula |
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula |
Maximizing the lifetime of embedded systems powered by fuel cell-battery hybrids. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
DVFS system, task scaling, hybrid systems, battery, fuel cell |
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Chaitali Chakrabarti, Naehyuck Chang |
An optimal analytical solution for processor speed control with thermal constraints. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
optimal control, temperature, DVFS, thermal management, DTM |
| 1 | Praveen Ghanta, Sarma B. K. Vrudhula, Sarvesh Bhardwaj, Rajendran Panda |
Stochastic variational analysis of large power grids considering intra-die correlations. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
orthonormal polynomials, correlations, process variations, power grids, stochastic analysis, polynomial chaos |
| 1 | Youngjin Cho, Naehyuck Chang, Chaitali Chakrabarti, Sarma B. K. Vrudhula |
High-level power management of embedded systems with application-specific energy cost functions. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
algorithms |
| 1 | Jianli Zhuo, Chaitali Chakrabarti, Naehyuck Chang, Sarma B. K. Vrudhula |
Extending the lifetime of fuel cell based hybrid systems. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
DVFS system, task scaling, hybrid systems, battery, fuel cell |
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Praveen Ghanta, Yu Cao |
Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
Karhunen-Loeve, intra-die, correlations, process variations, statistical, leakage |
| 1 | Sarvesh Bhardwaj, Yu Cao, Sarma B. K. Vrudhula |
Statistical leakage minimization through joint selection of gate sizes, gate lengths and threshold voltage. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Praveen Ghanta, Sarma B. K. Vrudhula |
A framework for statistical timing analysis using non-linear delay and slew models. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw |
Probability distribution of signal arrival times using Bayesian networks. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Krzysztof S. Berezowski, Sarma B. K. Vrudhula |
Automatic Design of Binary and Multiple-Valued Logic Gates on RTD Series. |
DSD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Energy optimal speed control of devices with discrete speed sets. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
low-power, functions, convex, voltage scaling, energy optimization, frequency scaling, speed control |
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
optimization, statistical, leakage, geometric programming |
| 1 | Praveen Ghanta, Sarma B. K. Vrudhula, Rajendran Panda, Janet Meiling Wang |
Stochastic Power Grid Analysis Considering Process Variations. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Battery optimization vs energy optimization: which to choose and when? |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula |
Formalizing designer's preferences for multiattribute optimization with application to leakage-delay tradeoffs. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Tao Shu, Marwan Krunz, Sarma B. K. Vrudhula |
Power balanced coverage-time optimization for clustered wireless sensor networks. |
MobiHoc |
2005 |
DBLP DOI BibTeX RDF |
coverage time, signomial optimization, clustering, sensor networks, topology control, generalized geometric programming |
| 1 | Kaviraj Chopra, Sarma B. K. Vrudhula |
Implicit pseudo boolean enumeration algorithms for input vector control. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods |
| 1 | Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula |
Variational delay metrics for interconnect timing analysis. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
Performance, Design |
| 1 | Sreeja Raj, Sarma B. K. Vrudhula, Janet Meiling Wang |
A methodology to improve timing yield in the presence of process variations. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
timing analysis, gate sizing, timing yield |
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Musaravakkam S. Krishnan |
Disk drive energy optimization for audio-video applications. |
CASES |
2004 |
DBLP DOI BibTeX RDF |
multimedia, low power, disk drive, speed control |
| 1 | Raghukiran Sreeramaneni, Sarma B. K. Vrudhula |
Energy Profiler for Hardware/Software Co-Design. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj |
Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sridhar Dasika, Sarma B. K. Vrudhula, Kaviraj Chopra, R. Srinivasan |
A Framework for Battery-Aware Sensor Management. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula |
Energy optimization for a two-device data flow chain. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Janet Meiling Wang, Praveen Ghanta, Sarma B. K. Vrudhula |
Stochastic analysis of interconnect performance in the presence of process variations. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
Energy management for battery-powered embedded systems. |
ACM Trans. Embedded Comput. Syst. |
2003 |
DBLP DOI BibTeX RDF |
scheduling, modeling, low-power design, voltage scaling, Battery |
| 1 | Sarma B. K. Vrudhula, David T. Blaauw, Supamas Sirichotiyakul |
Probabilistic analysis of interconnect coupling noise. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov |
Battery Modeling for Energy-Aware System Design. |
IEEE Computer |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach |
A model for battery lifetime analysis for organizing applications on a pocket computer. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ravishankar Rao, Sarma B. K. Vrudhula, Daler N. Rakhmatov |
Analysis of discharge techniques for multiple battery systems. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
discharge technique, multiple battery, lifetime optimization |
| 1 | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Computation and Refinement of Statistical Bounds on Circuit Delay. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical Timing Analysis Using Bounds. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw |
AU: Timing Analysis Under Uncertainty. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Haibo Wang, Sarma B. K. Vrudhula |
Behavioral synthesis of field programmable analog array circuits. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
Programmable circuits, analog synthesis |
| 1 | Qi Wang, Sarma B. K. Vrudhula |
Algorithms for minimizing standby power in deep submicrometer, dual-Vt CMOS circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Deborah A. Wallach |
Battery lifetime prediction for energy-aware computing. |
ISLPED |
2002 |
DBLP DOI BibTeX RDF |
modeling, low-power design, battery |
| 1 | Sarma B. K. Vrudhula, David Blaauw, Supamas Sirichotiyakul |
Estimation of the likelihood of capacitive coupling noise. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
noise, signal integrity, deep submicron |
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Chaitali Chakrabarti |
Battery-conscious task sequencing for portable devices including voltage/clock scaling. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
scheduling, modeling, low-power design, voltage scaling, battery |
| 1 | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Aseem Agarwal, David Blaauw, Vladimir Zolotov, Sarma B. K. Vrudhula |
Statistical timing analysis using bounds and selective enumeration. |
Timing Issues in the Specification and Synthesis of Digital Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula, David Blaauw |
Estimation of signal arrival times in the presence of delay noise. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
Hardware-software bipartitioning for dynamically reconfigurable systems. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
network flows, reconfigurable systems, hardware-software partitioning |
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
Time-to-failure estimation for batteries in portable electronic systems. |
ISLPED |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
Minimizing routing configuration cost in dynamically reconfigurable FPGAs. |
IPDPS |
2001 |
DBLP BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula |
An Analytical High-Level Battery Model for Use in Energy Management of Portable Electronic Systems. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Daler N. Rakhmatov, Sarma B. K. Vrudhula, Thomas J. Brown, Ajay Nagarandal |
Adaptive Multiuser Online Reconfigurable Engine. |
IEEE Design & Test of Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Qi Wang, Sarma B. K. Vrudhula, Gary K. H. Yeap, Shantanu Ganguly |
Power reduction and power-delay trade-offs using logic transformations. |
ACM Trans. Design Autom. Electr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
CMOS logic, low power, logic synthesis, power estimation, logic optimization |
| 1 | Qi Wang, Sarma B. K. Vrudhula |
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
low power, CMOS circuits, dual Vt |
| 1 | Qi Wang, Sarma B. K. Vrudhula |
Data Driven Power Optimization of Sequential Circuits. |
DATE |
1998 |
DBLP DOI BibTeX RDF |
logic synthesis low power design sequential circuits digital circuit testing verification |
| 1 | Qi Wang, Sarma B. K. Vrudhula |
Static power optimization of deep submicron CMOS circuits for dual VT technology. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Qi Wang, Sarma B. K. Vrudhula, Shantanu Ganguly |
An Investigation of Power Delay Trade-Offs on PowerPC Circuits. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
Formal Verification Using Edge-Valued Binary Decision Diagrams. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
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