Search results for "Sean Safarpour"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Andrew C. Ling, Stephen Dean Brown, Sean Safarpour, Jianwen Zhu	Toward Automated ECOs in FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Andreas G. Veneris, Brian Keng, Sean Safarpour	From RTL to silicon: The case for automated debug.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Brian Keng, Sean Safarpour, Andreas G. Veneris	Automated debugging of SystemVerilog assertions.	DATE	2011	DBLP DOI BibTeX RDF
1	Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour	Debugging with dominance: On-the-fly RTL debug solution implications.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Brian Keng, Sean Safarpour, Andreas G. Veneris	Bounded Model Debugging.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yibin Chen, Sean Safarpour, João Marques-Silva, Andreas G. Veneris	Automated Design Debugging With Maximum Satisfiability.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Yu-Shen Yang, Brian Keng, Nicola Nicolici, Andreas G. Veneris, Sean Safarpour	Automated silicon debug data analysis techniques for a hardware data acquisition environment.	ISQED	2010	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Farid N. Najm	Managing verification error traces with bounded model debugging.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Brian Keng, Andreas G. Veneris, Sean Safarpour	An Automated Framework for Correction and Debug of PSL Assertions.	MTV	2010	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris	Automated Design Debugging With Abstraction and Refinement.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris	Automated debugging with high level abstraction and refinement.	HLDVT	2009	DBLP DOI BibTeX RDF
1	Yibin Chen, Sean Safarpour, Andreas G. Veneris, João P. Marques Silva	Spatial and temporal design debug using partial MaxSAT.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	maximum satisfiability, design debugging
1	Andreas G. Veneris, Sean Safarpour	The day Sherlock Holmes decided to do EDA.	DAC	2009	DBLP DOI BibTeX RDF	error localization, verification, debugging
1	Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour	Towards automated ECOs in FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	pst, optimization, fpga, boolean satisfiability, resynthesis
1	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler	Improved SAT-based Reachability Analysis with Observability Don't Cares.	JSAT	2008	DBLP BibTeX RDF
1	Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah	Improved Design Debugging Using Maximum Satisfiability.	FMCAD	2007	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian	Trace Compaction using SAT-based Reachability Analysis.	ASP-DAC	2007	DBLP DOI BibTeX RDF
1	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir	Maximum circuit activity estimation using pseudo-boolean satisfiability.	DATE	2007	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris	Abstraction and refinement techniques in automated design debugging.	DATE	2007	DBLP DOI BibTeX RDF
1	Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith	A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan	Efficient SAT-based Boolean matching for FPGA technology mapping.	DAC	2006	DBLP DOI BibTeX RDF	FPGA technology mapping, Boolean satisfiability, Boolean matching
1	Görschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler	On the relation between simulation-based and SAT-based diagnosis.	DATE	2006	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler	Integrating observability don't cares in all-solution SAT solvers.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris	Abstraction and Refinement Techniques in Automated Design Debugging.	MTV	2006	DBLP DOI BibTeX RDF
1	Sean Safarpour, Görschwin Fey, Andreas G. Veneris, Rolf Drechsler	Utilizing don't care states in SAT-based bounded sequential problems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	don't care states, unreachable states, satisfiability, bounded model checking, sequential equivalence checking
1	Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour	Diagnosing multiple transition faults in the absence of timing information.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	diagnosis, multiple faults, delay faults, incremental, transition faults
1	Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler	Post-Verification Debugging of Hierarchical Designs.	MTV	2005	DBLP DOI BibTeX RDF
1	Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler	Post-verification debugging of hierarchical designs.	ICCAD	2005	DBLP BibTeX RDF
1	Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee	Managing Don't Cares in Boolean Satisfiability.	DATE	2004	DBLP DOI BibTeX RDF
1	Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith	Debugging Sequential Circuits Using Boolean Satisfiability.	MTV	2004	DBLP DOI BibTeX RDF
1	Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir	Debugging sequential circuits using Boolean satisfiability.	ICCAD	2004	DBLP DOI BibTeX RDF

Publications of "Sean Safarpour" ( http://dblp.L3S.de/Authors/Sean_Safarpour )