Search results for "Seiji Kajihara"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara	Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.	IEICE Transactions	2011	DBLP BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang	A novel scan segmentation design method for avoiding shift timing failure in scan testing.	ITC	2011	DBLP DOI BibTeX RDF
1	Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich	SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.	ISLPED	2011	DBLP BibTeX RDF
1	Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Yasuo Sato, Hisato Yamaguchi, Makoto Matsuzono, Seiji Kajihara	Multi-cycle Test with Partial Observation on Scan-Based BIST Structure.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor	Power-aware test generation with guaranteed launch safety for at-speed scan testing.	VTS	2011	DBLP DOI BibTeX RDF
1	Kohei Miyase, X. Wen, M. Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara	Transition-Time-Relation based capture-safety checking for at-speed scan test generation.	DATE	2011	DBLP BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor	High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja	A Study of Capture-Safe Test Generation Flow for At-Speed Testing.	IEICE Transactions	2010	DBLP BibTeX RDF
1	Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura	On estimation of NBTI-Induced delay degradation.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Hyunbean Yi, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato, Seiji Kajihara, Hideo Fujiwara	Aging test strategy and adaptive test scheduling for SoC failure prediction.	IOLTS	2010	DBLP DOI BibTeX RDF
1	Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara	A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.	PRDC	2009	DBLP DOI BibTeX RDF
1	Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, M. Aso, Hiroshi Furukawa	CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara	A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.	ICCAD	2009	DBLP BibTeX RDF
1	Seiji Kajihara, Michiko Inoue	Special Section on Test and Verification of VLSIs.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy	On Detection of Bridge Defects with Stuck-at Tests.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara	A Novel Per-Test Fault Diagnosis Method Based on the Extended X-Fault Model for Deep-Submicron LSI Circuits.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	At-speed scan testing, Capture switching activity, X-filling, Test cube, ATPG, Low power testing
1	X. Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, H. Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja	A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.	European Test Symposium	2008	DBLP DOI BibTeX RDF	At-Speed Scan Testing, Test Relaxation, X-Filling, Capture Mode, Yield Loss
1	Ilia Polian, Kohei Miyase, Yusuke Nakamura, Seiji Kajihara, Piet Engelke, Bernd Becker, Stefan Spinner, Xiaoqing Wen	Diagnosis of Realistic Defects Based on the X-Fault Model.	DDECS	2008	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara	Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Novel ATPG Method for Capture Power Reduction during Scan Testing.	IEICE Transactions	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang	A novel scheme to reduce power supply noise for high-quality at-speed scan testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja	Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing.	DAC	2007	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Masahiro Yamamoto, Xiaoqing Wen, Masayasu Fukunaga, Kazumi Hatayama, Takashi Aikyo	Estimation of delay test quality and its application to test generation.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita	A Per-Test Fault Diagnosis Method Based on the X-Fault Model.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara	A Statistical Quality Model for Delay Testing.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Irith Pomeranz, Shin-ya Kobayashi, Yuzo Takamatsu	On Finding Don't Cares in Test Sequences for Sequential Circuits.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	A New Method for Low-Capture-Power Test Generation for Scan Testing.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Shohei Morishima, Akane Takuma, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A Framework of High-quality Transition Fault ATPG for Scan Circuits.	ITC	2006	DBLP DOI BibTeX RDF
1	Masayasu Fukunaga, Seiji Kajihara, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	A dynamic test compaction procedure for high-quality path delay testing.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita	A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.	VTS	2006	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja	Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.	ICCD	2006	DBLP BibTeX RDF
1	Xiaoqing Wen, Tatsuya Suzuki, Seiji Kajihara, Kohei Miyase, Yoshihiro Minamoto, Laung-Terng Wang, Kewal K. Saluja	Efficient Test Set Modification for Capture Power Reduction.	J. Low Power Electronics	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Seiji Kajihara, Hideo Tamamoto, Kewal K. Saluja, Kozo Kinoshita	On Design for IDDQ-Based Diagnosability of CMOS Circuits Using Multiple Power Supplies.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka	On Statistical Estimation of Fault Efficiency for Path Delay Faults Based on Untestable Path Analysis.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu	Test cost reduction for logic circuits: Reduction of test data volume and test application time.	Systems and Computers in Japan	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	Low-capture-power test generation for scan-based at-speed testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara	Invisible delay quality - SDQM model lights up what could not be seen.	ITC	2005	DBLP DOI BibTeX RDF
1	Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy	On Improving Defect Coverage of Stuck-at Fault Tests.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, Toshiyuki Maeda, Shuji Hamada, Yasuo Sato	Path delay test compaction with process variation tolerance.	DAC	2005	DBLP DOI BibTeX RDF	process variation, delay testing, path delay fault, test compaction
1	Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Seiji Kajihara	Evaluation of the statistical delay quality model.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yasumi Doi, Seiji Kajihara, Xiaoqing Wen, Lei Li, Krishnendu Chakrabarty	Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On Low-Capture-Power Test Generation for Scan Testing.	VTS	2005	DBLP DOI BibTeX RDF
1	Lei Li, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy	Don't Care Identification and Statistical Encoding for Test Data Compression.	IEICE Transactions	2004	DBLP BibTeX RDF
1	Kohei Miyase, Seiji Kajihara	XID: Don't care identification of test patterns for combinational circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu	Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy	Multiple Scan Tree Design with Test Vector Modification.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara	Random Access Scan: A solution to test power, test data volume and test time.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita	On per-test fault diagnosis using the X-fault model.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On test data volume reduction for multiple scan chain designs.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	Decompressor, Don't care identification, Encoding techniques, Design for testability, Test data compression
1	Takeshi Asakawa, Kazuhiko Iwasaki, Seiji Kajihara	BIST-oriented test pattern generator for detection of transition faults.	Systems and Computers in Japan	2003	DBLP DOI BibTeX RDF
1	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electronic Testing	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
1	Kohei Miyase, Seiji Kajihara	Optimal Scan Tree Construction with Test Vector Modification for Test Compression.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Masayasu Fukunaga, Seiji Kajihara, Sadami Takeoka	On Estimation of Fault Efficiency for Path Delay Faults.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu, Seiji Kajihara, Irith Pomeranz	A Method to Find Don't Care Values in Test Sequences for Sequential Circuits.	ICCD	2003	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Yasumi Doi, Lei Li, Krishnendu Chakrabarty	On Combining Pinpoint Test Set Relaxation and Run-Length Codes for Reducing Test Data Volume.	ICCD	2003	DBLP DOI BibTeX RDF
1	Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita	On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.	ITC	2002	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy	Test Data Compression Using Don't-Care Identification and Statistical Encoding.	DELTA	2002	DBLP DOI BibTeX RDF	Statistical Encoding, Don't Care Identification, Huffman's algorithm, Test Data Compression
1	Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy	A Method of Static Test Compaction Based on Don't Care Identification.	DELTA	2002	DBLP DOI BibTeX RDF	Coloring Problem, Don't Care Identification, ATPG, Static Test Compaction
1	Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy	Test Data Compression Using Don?t-Care Identification and Statistical Encoding.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	don´t care identification, Huffman´s algorithm, test generation, test compression
1	Seiji Kajihara, Koji Ishida, Kohei Miyase	Test Vector Modification for Power Reduction during Scan Testing.	VTS	2002	DBLP DOI BibTeX RDF
1	Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz	On Test Data Volume Reduction for Multiple Scan Chain Designs.	VTS	2002	DBLP DOI BibTeX RDF
1	Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy	Don't-Care Identification on Specific Bits of Test Patterns.	ICCD	2002	DBLP DOI BibTeX RDF
1	Yun Shao 0002, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz	An Efficient Method to Identify Untestable Path Delay Faults.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara	Hybrid BIST Using Partially Rotational Scan.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Kohei Miyase	On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits.	ICCAD	2001	DBLP BibTeX RDF
1	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta	On validating data hold times for flip-flops in sequential circuits.	ITC	2000	DBLP DOI BibTeX RDF
1	Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy	Selection of potentially testable path delay faults for test generation.	ITC	2000	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy	Enhanced untestable path analysis using edge graphs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	untestable path analysis, edge graphs, partial path sensitization, edge graph, logic testing, logic circuits, logic circuits, path delay fault testing
1	Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko	On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	IDDQ testing, test compaction
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On Test Generation with A Limited Number of Tests.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita	An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Kewal K. Saluja	On Test Pattern Compaction Using Random Pattern Fault Simulation.	VLSI Design	1998	DBLP DOI BibTeX RDF	test generation, combinational circuit, fault simulation, stuck-at fault, test compaction
1	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	Compact test sets for high defect coverage.	IEEE Trans. on CAD of Integrated Circuits and Systems	1997	DBLP DOI BibTeX RDF
1	Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita	A diagnosis method for single logic design errors in gate-level combinational circuits.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara	On invariant implication relations for removing partial circuits.	Systems and Computers in Japan	1997	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis of Sequential Circuits by Redundancy Removal and Retiming.	J. Electronic Testing	1997	DBLP DOI BibTeX RDF	synthesis of sequential circuits, sequentially redundant fault, retiming, redundant fault, redundancy removal
1	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
1	Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy	A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths.	VLSI Design	1997	DBLP DOI BibTeX RDF	robust dependent path, local circuit analysis, logic circuit testing, functionally unsensitizable path, timing, logic circuits
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
1	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On the effects of test compaction on defect coverage.	VTS	1996	DBLP DOI BibTeX RDF	surrogate faults, fault diagnosis, test generation, integrated circuit testing, fault modeling, test sets, test compaction, defect coverage
1	Seiji Kajihara, Rikiya Nishigaya, Tetsuji Sumioka, Kozo Kinoshita	Acceleration Techniques of Multiple Fault Test Generation Using Vector Pair Analysis.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Retiming for Sequential Circuits with a Specified Initial State and Its Application to Testability Enhancement.	IEICE Transactions	1995	DBLP BibTeX RDF
1	Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy	Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	1995	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Partial scan design and test sequence generation based on reduced scan shift method.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	partial scan circuit, short test sequence, reduced scan shift, scan design, test sequence generation
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Test sequence compaction by reduced scan shift and retiming.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	reduced scan shift, full scan designed circuits, computational complexity, logic testing, transformation, timing, design for testability, sequential circuits, sequential circuit, logic CAD, flip-flops, flip-flops, retiming, computing time, test length, test sequence generation, test sequence compaction
1	Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara	Compact test generation for bridging faults under I/sub DDQ/ testing.	VTS	1995	DBLP DOI BibTeX RDF	compact test generation, bit-adders, logic testing, partitioning, integrated circuit testing, fault location, stuck-at faults, CMOS logic circuits, bridging faults, logic partitioning, I/sub DDQ/ testing
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Resynthesis for sequential circuits designed with a specified initial state.	VTS	1995	DBLP DOI BibTeX RDF	specified initial state, retiming method, redundancy removal method, resynthesized circuit, input sequences, logic optimisation, timing, redundancy, sequential circuits, logic CAD, flip-flops, flip-flops, circuit optimisation, synchronous sequential circuits
1	Hiroyuki Yotsuyanagi, Seiji Kajihara, Kozo Kinoshita	Synthesis for Testability by Sequential Redundancy Removal Using Retiming.	FTCS	1995	DBLP DOI BibTeX RDF
1	Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita	Reduced Scan Shift: A New Testing Method for Sequential Circuit.	ITC	1994	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy	Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits.	DAC	1993	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Tetsuji Sumioka, Kozo Kinoshita	Test generation for multiple faults based on parallel vector pair analysis.	ICCAD	1993	DBLP DOI BibTeX RDF
1	Seiji Kajihara, Haruko Shiba, Kozo Kinoshita	Removal of Redundancy in Logic Circuits under Classification of Undetectable Faults.	FTCS	1992	DBLP DOI BibTeX RDF

Publications of "Seiji Kajihara" ( http://dblp.L3S.de/Authors/Seiji_Kajihara )