|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 15 occurrences of 13 keywords
|
|
|
|
|
Results
Found 27 publication records. Showing 27 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung |
A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Jisu Kim, Jee-Hwan Song, Seung-Hyuk Kang, Sei-Seung Yoon, Seong-Ook Jung |
Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
|
| 1 | Heechai Kang, Kyungho Ryu, DongHwan Lee, Won Lee, SuHo Kim, JongRyun Choi, Seong-Ook Jung |
Process variation tolerant all-digital multiphase DLL for DDR3 interface. |
CICC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mingu Kang, Seong-Ook Jung |
Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD). |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy |
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Sei-Seung Yoon |
Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunwoo Nho, Sei-Seung Yoon, S. Simon Wong, Seong-Ook Jung |
Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy |
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
signal slope, interconnect, gate delay, subthreshold operation |
| 1 | Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A 32-bit carry lookahead adder using dual-path all-N logic. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang |
Minimum delay optimization for domino circuits - a coupling-aware approach. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
Logic synthesis, coupling, domino logic, delay minimization |
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Timing constraints for domino logic gates with timing-dependent keepers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang |
Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware interconnect power optimization in domino logic synthesis. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained transistor sizing and power optimization for dual Vst domino logic. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
keeper, optimal timing, noise, skew, domino logic, dynamic circuit |
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage |
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang |
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang |
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang |
New current-mode sense amplifiers for high density DRAM and PIM architectures. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang |
Skew-tolerant high-speed (STHS) domino logic. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang |
Coupling-aware minimum delay optimization for domino logic circuits. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang |
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained power optimization for dual VT domino logic. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware power optimization for on-chip interconnect. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #27 of 27 (100 per page; Change: )
|
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")