Search results for "Serge Pravossoudovitch"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL [InlineMediaObject not available: see fulltext.] eFlash Memories.	J. Electronic Testing	2012	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	On using address scrambling to implement defect tolerance in SRAMs.	ITC	2011	DBLP DOI BibTeX RDF
1	Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine	Failure Analysis and Test Solutions for Low-Power SRAMs.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits.	Asian Test Symposium	2011	DBLP DOI BibTeX RDF
1	Miroslav Valka, Alberto Bosio, Luigi Dilillo, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing.	European Test Symposium	2011	DBLP DOI BibTeX RDF	At-speed delay fault testing, Power-aware Testing, Functional power
1	Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults.	DFT	2011	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector.	DFT	2011	DBLP DOI BibTeX RDF
1	Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	A study of path delay variations in the presence of uncorrelated power and ground supply noise.	DDECS	2011	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	On using a SPICE-like TSTAC™ eFlash model for design and test.	DDECS	2011	DBLP DOI BibTeX RDF
1	Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling.	DDECS	2011	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects.	IEEE Trans. Computers	2010	DBLP DOI BibTeX RDF	Diagnosis, fault modeling, fault simulation, circuit simulation, critical path tracing
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed	Is test power reduction through X-filling good enough?	ITC	2010	DBLP DOI BibTeX RDF
1	D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich	Parity prediction synthesis for nano-electronic gate designs.	ITC	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Impact of Resistive-Bridging Defects in SRAM Core-Cell.	DELTA	2010	DBLP DOI BibTeX RDF	core-cell, resistive-bridging defects, SRAM
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An Exact and Efficient Critical Path Tracing Algorithm.	DELTA	2010	DBLP DOI BibTeX RDF	Fault models, Fault Simulation, Critical Path Tracing
1	Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer	A Comprehensive System-on-Chip Logic Diagnosis.	Asian Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	A statistical simulation method for reliability analysis of SRAM core-cells.	DAC	2010	DBLP DOI BibTeX RDF	SRAM core-cell, Monte-Carlo, reliability analysis
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Setting test conditions for improving SRAM reliability.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez	A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction.	European Test Symposium	2010	DBLP DOI BibTeX RDF
1	Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Pierre Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine	Detecting NBTI induced failures in SRAM core-cells.	VTS	2010	DBLP DOI BibTeX RDF
1	Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes.	DDECS	2010	DBLP DOI BibTeX RDF
1	Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Is triple modular redundancy suitable for yield improvement?	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis of Resistive-Open Defects in SRAM Sense Amplifiers.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash.	J. Electronic Testing	2009	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	A case study on logic diagnosis for System-on-Chip.	ISQED	2009	DBLP DOI BibTeX RDF
1	Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard	NAND flash testing: A preliminary study on actual defects.	ITC	2009	DBLP DOI BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer	Delay Fault Diagnosis in Sequential Circuits.	Asian Test Symposium	2009	DBLP DOI BibTeX RDF
1	Alexandre Ney, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A new design-for-test technique for SRAM core-cell stability faults.	DATE	2009	DBLP BibTeX RDF
1	Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute	Comprehensive bridging fault diagnosis based on the SLAT paradigm.	DDECS	2009	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda	An efficient fault simulation technique for transition faults in non-scan sequential circuits.	DDECS	2009	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Zhanglei Wang, Patrick Girard, Krishnendu Chakrabarty, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	DfT, Scan, Test data compression, Low power testing
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	SoC Yield Improvement: Redundant Architectures to the Rescue?	ITC	2008	DBLP DOI BibTeX RDF
1	Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs.	ITC	2008	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Improving Diagnosis Resolution without Physical Information.	DELTA	2008	DBLP DOI BibTeX RDF	Logic Diagnosis, Fault Modeling, Path Tracing
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing.	VTS	2008	DBLP DOI BibTeX RDF	write driver, design-for-diagnosis, diagnosis, SRAM
1	Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian, Vincent Gouin	A Design-for-Diagnosis Technique for SRAM Write Drivers.	DATE	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Using TMR Architectures for Yield Improvement.	DFT	2008	DBLP DOI BibTeX RDF
1	Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi	SoC Symbolic Simulation: a case study on delay fault testing.	DDECS	2008	DBLP DOI BibTeX RDF
1	Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Yield Improvement, Fault-Tolerance to the Rescue?.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits.	J. Electronic Testing	2007	DBLP DOI BibTeX RDF	Resistive-open defects, Pre-charge circuits, Memory testing, Dynamic faults
1	Olivier Ginez, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Jean Michel Daga	A concurrent approach for testing address decoder faults in eFlash memories.	ITC	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	DERRIC: A Tool for Unified Logic Diagnosis.	European Test Symposium	2007	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs.	VTS	2007	DBLP DOI BibTeX RDF
1	Alexandre Ney, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Slow write driver faults in 65nm SRAM technology: analysis and March test solution.	DATE	2007	DBLP DOI BibTeX RDF
1	Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Mixed Approach for Unified Logic Diagnosis.	DDECS	2007	DBLP BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	A Gated Clock Scheme for Low Power Testing of Logic Cores.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	test-per-scan, test-per-clock, low power design, low power test
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	BIST, delay faults, look-up table
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions.	J. Electronic Testing	2006	DBLP DOI BibTeX RDF	address decoders, memory testing, dynamic faults
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich	Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Olivier Ginez, Jean Michel Daga, Marylene Combe, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	An Overview of Failure Mechanisms in Embedded Flash Memories.	VTS	2006	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit.	DDECS	2006	DBLP BibTeX RDF
1	Simone Borri, Magali Bastian Hage-Hassan, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel	Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	address decoders, core-cells, memory testing, dynamic faults
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	look-up table (LUT), FPGA, test, delay fault
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories.	J. Electronic Testing	2005	DBLP DOI BibTeX RDF	SRAM core-cell, resistive open defects, memory testing, March test, dynamic faults
1	Nabil Badereddine, Patrick Girard, Arnaud Virazel, Serge Pravossoudovitch, Christian Landrault	Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Christian Landrault	Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian Hage-Hassan	Data Retention Fault in SRAM Memories: Analysis and Detection Procedures.	VTS	2005	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Power-Driven Routing-Constrained Scan Chain Design.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	scan chain design, DfT, low power testing, scan testing
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DELTA	2004	DBLP DOI BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs.	DELTA	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan	Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	March iC-: An Improved Version of March C- for ADOFs Detection.	VTS	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Design of Routing-Constrained Low Power Scan Chains.	DATE	2004	DBLP DOI BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs.	IOLTS	2004	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.	ITC	2003	DBLP DOI BibTeX RDF
1	Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri	Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
1	Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Defect Analysis for Delay-Fault BIST in FPGAs.	IOLTS	2003	DBLP DOI BibTeX RDF
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Hardware Generation of Random Single Input Change Test Sequences.	J. Electronic Testing	2002	DBLP DOI BibTeX RDF	single input change, generation, hardware, random testing, test sequence
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich	High Defect Coverage with Low-Power Test Sequences in a BIST Environment.	IEEE Design & Test of Computers	2002	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Power Driven Chaining of Flip-Flops in Scan Architectures.	ITC	2002	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Test Power: a Big Issue in Large SOC Designs.	DELTA	2002	DBLP DOI BibTeX RDF	DfT, BIST, Scan, Low Power Testing, Test Power
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	On Using Efficient Test Sequences for BIST.	VTS	2002	DBLP DOI BibTeX RDF
1	Arnaud Virazel, René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences.	J. Electronic Testing	2001	DBLP DOI BibTeX RDF	non-robust test, BIST, random testing, delay testing, robust test
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
1	René David, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Random Adjacent Sequences: An Efficient Solution for Logic BIST.	VLSI-SOC	2001	DBLP BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Hans-Joachim Wunderlich	A Modified Clock Scheme for a Low Power BIST Test Pattern Generator.	VTS	2001	DBLP DOI BibTeX RDF
1	Yannick Bonhomme, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Gated Clock Scheme for Low Power Scan-Based BIST.	IOLTW	2001	DBLP DOI BibTeX RDF
1	Salvador Manich, A. Gabarró, M. Lopez, Joan Figueras, Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Paulo J. Teixeira, Marcelino B. Santos	Low Power BIST by Filtering Non-Detecting Vectors.	J. Electronic Testing	2000	DBLP DOI BibTeX RDF	low power BIST, low energy consumption, LFSR, gated clock
1	Patrick Girard, Christian Landrault, Loïs Guiller, Serge Pravossoudovitch	Low power BIST design by hypergraph partitioning: methodology and architectures.	ITC	2000	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	An adjacency-based test pattern generator for low power BIST design.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	low-power electronics, adjacency-based test pattern generator, low power BIST design, pseudo-random TPG, test-per-clock BIST, peak power consumption, total energy consumption, strongly connected circuits, VLSI, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, test length
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults.	IOLTW	2000	DBLP DOI BibTeX RDF	BIST, Random Testing, Delay Testing, Bridging Faults
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A Scan-BIST Structure to Test Delay Faults in Sequential Circuits.	J. Electronic Testing	1999	DBLP DOI BibTeX RDF	BIST, delay faults, scan design
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	test vector ordering, test, low power, switching activity
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	A Test Vector Inhibiting Technique for Low Energy BIST Design.	VTS	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch, Joan Figueras, Salvador Manich, Paulo J. Teixeira, Marcelino B. Santos	Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity.	ISCAS	1999	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch, Arnaud Virazel	A BIST Structure to Test Delay Faults in a Scan Environment.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac	A non-iterative gate resizing algorithm for high reduction in power consumption.	Integration	1997	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac	A gate resizing technique for high reduction in power consumption.	ISLPED	1997	DBLP DOI BibTeX RDF
1	Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch	An optimized BIST test pattern generator for delay testing.	VTS	1997	DBLP DOI BibTeX RDF	BIST test pattern generator, robust delay fault coverage, single input change test sequence, compatible inputs, optimization, delays, built-in self-test, fault detection, delay testing, test length, area overhead, circuit under test
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch, B. Rodriguez	A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms.	ITC	1996	DBLP DOI BibTeX RDF
1	S. Cremoux, Christophe Fagot, Patrick Girard, Christian Landrault, Serge Pravossoudovitch	A new test pattern generation method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	test pattern generation method, directed random generation technique, random test vectors, test sequence length, delay fault coverage, learning (artificial intelligence), VLSI, logic testing, delays, built-in self test, integrated circuit testing, BIST, automatic testing, delay fault testing, digital integrated circuits, learning tool, high speed circuits
1	Patrick Girard, Christian Landrault, Serge Pravossoudovitch	An advanced diagnostic method for delay faults in combinational faulty circuits.	J. Electronic Testing	1995	DBLP DOI BibTeX RDF	simulation, diagnosis, delay fault, critical path tracing

Publications of "Serge Pravossoudovitch" ( http://dblp.L3S.de/Authors/Serge_Pravossoudovitch )