Search results for "Seungwhun Paik"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin	HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Lee-eun Yu, Changsik Shin, Seungwhun Paik, Jing-Jia Liou, Youngsoo Shin	Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks.	Journal of Circuits, Systems, and Computers	2011	DBLP DOI BibTeX RDF
1	Seungwhun Paik, Seonggwan Lee, Youngsoo Shin	Retiming Pulsed-Latch Circuits With Regulating Pulse Width.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Seungwhun Paik	Pulsed-Latch Circuits: A New Dimension in ASIC Design.	IEEE Design & Test of Computers	2011	DBLP DOI BibTeX RDF
1	Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin	Pulser gating: A clock gating of pulsed-latch circuits.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin	Selectively patterned masks: Structured ASIC with asymptotically ASIC performance.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Seungwhun Paik, Gi-Joon Nam, Youngsoo Shin	Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin	HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Hyein Lee, Seungwhun Paik, Youngsoo Shin	Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Seungwhun Paik, Sangmin Kim, Youngsoo Shin	Wakeup synthesis and its buffered tree construction for power gating circuit designs.	ISLPED	2010	DBLP DOI BibTeX RDF	wakeup synthesis, leakage, power gating
1	Seungwhun Paik, Lee-eun Yu, Youngsoo Shin	Statistical time borrowing for pulsed-latch circuit designs.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Jun Seomun, Seungwhun Paik, Youngsoo Shin	Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim	Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Insup Shin, Seungwhun Paik, Youngsoo Shin	Register allocation for high-level synthesis using dual supply voltages.	DAC	2009	DBLP DOI BibTeX RDF	low power, high-level synthesis, register allocation, dual supply voltage
1	Seungwhun Paik, Insup Shin, Youngsoo Shin	HLS-l: High-level synthesis of high performance latch-based circuits.	DATE	2009	DBLP BibTeX RDF
1	Seonggwan Lee, Seungwhun Paik, Youngsoo Shin	Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits.	ICCAD	2009	DBLP BibTeX RDF
1	Seungwhun Paik, Youngsoo Shin	Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements.	DAC	2008	DBLP DOI BibTeX RDF	sleep vector, zigzag power gating, low power, leakage current, standard-cell
1	Jinseob Jeong, Seungwhun Paik, Youngsoo Shin	Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Hyein Lee, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF

Publications of "Seungwhun Paik" ( http://dblp.L3S.de/Authors/Seungwhun_Paik )