|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 5 occurrences of 5 keywords
|
|
|
|
|
Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Houman Homayoun, Mehryar Rahmatian, Vasileios Kontorinis, Shahin Golshan, Dean M. Tullsen |
Hot peripheral thermal management to mitigate cache temperature variation.  |
ISQED  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shahin Golshan, Hessam Kooti, Elaheh Bozorgzadeh |
SEU-Aware High-Level Data Path Synthesis and Layout Generation on SRAM-Based FPGAs.  |
IEEE Trans. on CAD of Integrated Circuits and Systems  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari |
MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits.  |
IEEE Trans. VLSI Syst.  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shahin Golshan, Love Singhal, Eli Bozorgzadeh |
Process variation aware system-level load assignment for total energy minimization using stochastic ordering.  |
ISQED  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shahin Golshan, Amin Khajeh, Houman Homayoun, Eli Bozorgzadeh, Ahmed M. Eltawil, Fadi J. Kurdahi |
Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.  |
CODES+ISSS  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, Alexander V. Veidenbaum, Fadi J. Kurdahi |
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks.  |
ISQED  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shahin Golshan, Eli Bozorgzadeh, Benjamin Carrión Schäfer, Kazutoshi Wakabayashi, Houman Homayoun, Alexander V. Veidenbaum |
Exploiting power budgeting in thermal-aware dynamic placement for reconfigurable systems.  |
ISLPED  |
2010 |
DBLP DOI BibTeX RDF |
computer aided design, placement, dynamic reconfiguration, temperature, reconfigurable systems |
| 1 | Shahin Golshan, Eli Bozorgzadeh |
SEU-aware resource binding for modular redundancy based designs on FPGAs.  |
DATE  |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shahin Golshan, Elaheh Bozorgzadeh |
Single-Event-Upset (SEU) Awareness in FPGA Routing.  |
DAC  |
2007 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #9 of 9 (100 per page; Change: )
|
|