Search results for "Shannon expansion"

Found 8 publication records. Showing 8 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
1	Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Meimand, Swarup Bhunia	Low power synthesis of dynamic logic circuits using fine-grained clock gating.	DATE	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy	A novel synthesis approach for active leakage power reduction using dynamic supply gating.	DAC	2005	DBLP DOI BibTeX RDF
1	Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai	Bipartitioning and encoding in low-power pipelined circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Low-power design
1	Kun-Lin Tsai, Feipei Lai, Shanq-Jang Ruan, Szu-Wei Chaung	State Reordering for Low Power Combinational Logic.	Asia-Pacific Computer Systems Architecture Conference	2003	DBLP DOI BibTeX RDF
1	Pramit Chavda, James Jacob, Vishwani D. Agrawal	Optimizing Logic Design Using Boolean Transforms.	VLSI Design	1998	DBLP DOI BibTeX RDF	multi-level synthesis, Boolean functions, logic design, logic synthesis
1	Adel Belhaouane, Yvon Savaria, Bozena Kaminska, Daniel Massicotte	Reconstruction method for jitter tolerant data acquisition system.	J. Electronic Testing	1996	DBLP DOI BibTeX RDF	nonuniform, jitter, signal reconstruction

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