Search results for "Shawki Areibi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Antony W. Savich, Medhat Moussa, Shawki Areibi	A scalable pipelined architecture for real-time computation of MLP-BP neural networks.	Microprocessors and Microsystems - Embedded Hardware Design	2012	DBLP DOI BibTeX RDF
1	Maxwell Walton, Omar Ahmed, Gary William Grewal, Shawki Areibi	An Empirical Investigation on System and Statement Level Parallelism Strategies for Accelerating Scatter Search Using Handel-C and Impulse-C.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi, Karanvir Chattha, Ben Kelly	PCIU: Hardware Implementations of an Efficient Packet Classification Algorithm with an Incremental Update Capability.	Int. J. Reconfig. Comp.	2011	DBLP DOI BibTeX RDF
1	M. Xu, Gary Gréwal, Shawki Areibi	StarPlace: A new analytic method for FPGA placement.	Integration	2011	DBLP DOI BibTeX RDF
1	Omar Ahmed, Shawki Areibi	GBSA: A group based search algorithm for packet classification.	IWCMC	2011	DBLP DOI BibTeX RDF
1	Ahmed Elhossini, Shawki Areibi, Robert Dony	Strength Pareto Particle Swarm Optimization and Hybrid EA-PSO for Multi-Objective Optimization.	Evolutionary Computation	2010	DBLP DOI BibTeX RDF
1	Ahmad Sghaier, Shawki Areibi, Robert Dony	Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms.	TRETS	2010	DBLP DOI BibTeX RDF
1	Ahmed Youssef, Zhen Yang, Mohab Anis, Shawki Areibi, Anthony Vannelli, Mohamed I. Elmasry	A Power-Efficient Multipin ILP-Based Routing Technique.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Ed Armstrong, Gary William Grewal, Shawki Areibi, Gerarda Darlington	An investigation of parallel memetic algorithms for VLSI circuit partitioning on multi-core computers.	CCECE	2010	DBLP DOI BibTeX RDF
1	Shawki Areibi, X. Bao, Gary Gréwal, Dilip K. Banerji, Peng Du	Meta-Heuristic Based Techniques for FPGA Placement: A Study.	I. J. Comput. Appl.	2009	DBLP BibTeX RDF
1	Logan M. Rakai, Laleh Behjat, Shawki Areibi, Tamás Terlaky	A Multilevel Congestion-Based Global Router.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Mahdi Elghazali, Ahmed Elhossini, Shawki Areibi	HW/SW co-design architecture exploration for VLSI maze routing.	CCECE	2009	DBLP DOI BibTeX RDF
1	Ming Xu, Gary Gréwal, Shawki Areibi, Charlie Obimbo, Dilip K. Banerji	Near-linear wirelength estimation for FPGA placement.	CCECE	2009	DBLP DOI BibTeX RDF
1	Ahmad Sghaier, Shawki Areibi, Robert Dony	IEEE802.16-2004 OFDM functions implementation on FPGAS with design exploration.	FPL	2008	DBLP DOI BibTeX RDF
1	Zhen Yang, Anthony Vannelli, Shawki Areibi	An ILP based hierarchical global routing approach for VLSI ASIC design.	Optimization Letters	2007	DBLP DOI BibTeX RDF	VLSI physical design, Standard cell global routing, Integer Linear Programming
1	Antony W. Savich, Medhat Moussa, Shawki Areibi	The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Stephen Coe, Shawki Areibi, Medhat Moussa	A hardware Memetic accelerator for VLSI circuit partitioning.	Computers & Electrical Engineering	2007	DBLP DOI BibTeX RDF
1	Shawki Areibi, Medhat Moussa, G. Koonar	A Genetic Algorithm Hardware Accelerator for VLSI Circuit Partitioning.	I. J. Comput. Appl.	2005	DBLP BibTeX RDF
1	Payam Ghafari, Ehsan Mirhadi, Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	A Low-Power Partitioning Methodology by Maximizing Sleep Time and Minimizing Cut Nets.	IWSOC	2005	DBLP DOI BibTeX RDF	Subthreshold Leakage Power, Sleep Time, Geometric Iterative Improvement, Genetic Algorithm, Partitioning, Segmented Trees
1	Shawki Areibi, Zhen Yang	Effective Memetic Algorithms for VLSI Design = Genetic Algorithms + Local Search + Multi-Level Clustering.	Evolutionary Computation	2004	DBLP DOI BibTeX RDF
1	Guangfa Lu, Shawki Areibi	An Island-Based GA Implementation for VLSI Standard-Cell Placement.	GECCO	2004	DBLP DOI BibTeX RDF
1	Peng Du, Gary William Grewal, Shawki Areibi, Dilip K. Banerji	A Fast Hierarchical Approach to FPGA Placement.	ESA/VLSI	2004	DBLP BibTeX RDF
1	Shawki Areibi, Anthony Vannelli	Tabu Search: Implementation & Complexity Analysis for Netlist Partitioning.	I. J. Comput. Appl.	2003	DBLP BibTeX RDF
1	Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	Design and optimization of multithreshold CMOS (MTCMOS) circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2003	DBLP DOI BibTeX RDF
1	Abdulnasser Younes, Hamada Ghenniwa, Shawki Areibi	An Adaptive Genetic Algorithm For Multi Objective Flexible Manufacturing Systems.	GECCO	2002	DBLP BibTeX RDF
1	Zhen Yang, Shawki Areibi	Global Placement Techniques for VLSI Physical Design Automation.	CAINE	2002	DBLP BibTeX RDF
1	G. Koonar, Shawki Areibi, Medhat Moussa	Hardware Implementation of Genetic Algorithms for VLSI Design.	CAINE	2002	DBLP BibTeX RDF
1	Kristian R. Nichols, Medhat Moussa, Shawki Areibi	Feasibility of Floating-Point Arithmetic in FPGA based ANNs.	CAINE	2002	DBLP BibTeX RDF
1	Hooman Homayounfar, Fangju Wang, Shawki Areibi	Advanced P2P Architecture Using Autonomous Agents.	CAINE	2002	DBLP BibTeX RDF
1	Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi	Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.	DAC	2002	DBLP DOI BibTeX RDF
1	Shawki Areibi, Matt Thompson	A new model for macrocell partitioning.	Computers and Their Applications	2001	DBLP BibTeX RDF
1	Hussein Etawil, Shawki Areibi, Anthony Vannelli	Attractor-repeller approach for global placement.	ICCAD	1999	DBLP BibTeX RDF
1	Shawki Areibi, Anthony Vannelli	Circuit Partitioning Using a Tabu Search Approach.	ISCAS	1993	DBLP BibTeX RDF

Publications of "Shawki Areibi" ( http://dblp.L3S.de/Authors/Shawki_Areibi )