Search results for "Sheldon X.-D. Tan"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hai Wang, Sheldon X.-D. Tan, Ryan Rakib	Compact Modeling of Interconnect Circuits over Wide Frequency Band by Adaptive Complex-Valued Sampling Method.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Fang Gong, Xuexin Liu, Hao Yu, Sheldon X.-D. Tan, Junyan Ren, Lei He	A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Zuying Luo, Guoxing Zhao, Joseph A. Gordon, Sheldon X.-D. Tan	Localized relaxation theory of circuits and its applications in electro-thermal analyses.	SCIENCE CHINA Information Sciences	2012	DBLP DOI BibTeX RDF
1	Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Duo Li, Eduardo H. Pacheco, Murli Tirumala, Lingli Wang	General Parameterized Thermal Modeling for High-Performance Microprocessor Design.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Lingfei Zhou, Jie Chen 0005, Ruijing Shen	Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports.	IEEE Trans. VLSI Syst.	2012	DBLP DOI BibTeX RDF
1	Xuexin Liu, Zao Liu, Sheldon X.-D. Tan, Joseph A. Gordon	Full-chip thermal analysis of 3D ICs with liquid cooling by GPU-accelerated GMRES method.	ISQED	2012	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Xuexin Liu	A new voltage binning technique for yield improvement based on graph theory.	ISQED	2012	DBLP DOI BibTeX RDF
1	Xuexin Liu, Sheldon X.-D. Tan, Zhigang Hao, Guoyong Shi	Time-domain performance bound analysis of analog circuits considering process variations.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Hai Wang, Sheldon X.-D. Tan, Xuexin Liu, Ashish Gupta	Runtime power estimator calibration for high-performance microprocessors.	DATE	2012	DBLP BibTeX RDF
1	Xuexin Liu, Sheldon X.-D. Tan, Hai Wang	Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach.	DATE	2012	DBLP BibTeX RDF
1	Xuexin Liu, Sheldon X.-D. Tan, Hai Wang, Hao Yu	A GPU-accelerated envelope-following method for switching power converter simulation.	DATE	2012	DBLP BibTeX RDF
1	Carlos Sánchez-López, Francisco V. Fernández, Esteban Tlelo-Cuautle, Sheldon X.-D. Tan	Pathological Element-Based Active Device Models and Their Application to Symbolic Analysis.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Zhigang Hao, Ruijing Shen, Sheldon X.-D. Tan, Bao Liu, Guoyong Shi, Yici Cai	Statistical full-chip dynamic power estimation considering spatial correlations.	ISQED	2011	DBLP DOI BibTeX RDF
1	Zhigang Hao, Sheldon X.-D. Tan, Guoyong Shi	An efficient statistical chip-level total power estimation method considering process variations with spatial correlation.	ISQED	2011	DBLP DOI BibTeX RDF
1	Zhigang Hao, Sheldon X.-D. Tan, Ruijing Shen, Guoyong Shi	Performance bound analysis of analog circuits considering process variations.	DAC	2011	DBLP DOI BibTeX RDF
1	Xuexin Liu, Hao Yu, Jacob Relles, Sheldon X.-D. Tan	A structured parallel periodic Arnoldi shooting algorithm for RF-PSS analysis based on GPU platforms.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Hai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta	Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Parameterized architecture-level dynamic thermal models for multicore microprocessors.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Jian Cui, Wenjian Yu, Yici Cai, Gengsheng Chen	Variational Capacitance Extraction and Modeling Based on Orthogonal Polynomial Method.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He, Sheldon X.-D. Tan	Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan	Passive Rational Interpolation-Based Reduction via Carathéodory Extension for General Systems.	IEEE Trans. on Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan	Statistical analysis of large on-chip power grid networks by variational reduction scheme.	Integration	2010	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Ning Mi, Yici Cai	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	Integration	2010	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear statistical analysis for full-chip leakage power with spatial correlation.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	statistical leakage analysis, strong and weak correlation, linear, look-up table
1	Kejie Ma, Lingli Wang, Xuegong Zhou, Sheldon X.-D. Tan, Jiarong Tong	General switch box modeling and optimization for FPGA routing architectures.	FPT	2010	DBLP DOI BibTeX RDF
1	Ruijing Shen, Sheldon X.-D. Tan, Jinjun Xiong	A linear algorithm for full-chip statistical leakage power analysis considering weak spatial correlation.	DAC	2010	DBLP DOI BibTeX RDF	statistical analysis, spatial correlation, dynamic power
1	Xuexin Liu, Hao Yu, Sheldon X.-D. Tan	A robust periodic arnoldi shooting algorithm for efficient analysis of large-scale RF/MM ICs.	DAC	2010	DBLP DOI BibTeX RDF	periodic steady-state analysis, shooting newton algorithm, Krylov subspace
1	Hai Wang, Sheldon X.-D. Tan, Gengsheng Chen	Wideband reduced modeling of interconnect circuits by adaptive complex-valued sampling method.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Hao Yu, Xuexin Liu, Hai Wang, Sheldon X.-D. Tan	A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Yici Cai	Efficient model reduction of interconnects via double gramians approximation.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai	Efficient power grid integrity analysis using on-the-fly error check and reduction.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Esteban Tlelo-Cuautle, Elyoenai Martínez-Romero, Carlos Sánchez-López, Sheldon X.-D. Tan	Symbolic behavioral modeling of low voltage amplifiers.	CCE	2010	DBLP DOI BibTeX RDF
1	Thom Jefferson A. Eguia, Sheldon X.-D. Tan, Ruijing Shen, Eduardo H. Pacheco, Murli Tirumala	General behavioral thermal modeling and characterization for multi-core microprocessor design.	DATE	2010	DBLP BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan	Fast Analysis of On-Chip Power Grid Circuits by Extended Truncated Balanced Realization Method.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Architecture-Level Thermal Characterization for Multicore Microprocessors.	IEEE Trans. VLSI Syst.	2009	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Boyuan Yan	Multiple block structure-preserving reduced order modeling of interconnect circuits.	Integration	2009	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Lifeng Wu	Hierarchical Krylov subspace based reduction of large interconnects.	Integration	2009	DBLP DOI BibTeX RDF
1	Thom Jefferson A. Eguia, Ning Mi, Sheldon X.-D. Tan	Statistical decoupling capacitance allocation by efficient numerical quadrature method.	ISQED	2009	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Wenting Hou, Liwei Ma, Sheldon X.-D. Tan, Pei-Hsin Ho, Xiaoyi Wang	GPU friendly fast Poisson solver for structured power grid network analysis.	DAC	2009	DBLP DOI BibTeX RDF	P/G network, fast Poisson solver, GPU
1	Hai Wang, Hao Yu, Sheldon X.-D. Tan	Fast analysis of nontree-clock network considering environmental uncertainty by parameterized and incremental macromodeling.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Gengsheng Chen, Xuan Zeng	Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Ruijing Shen, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical modeling and analysis of chip-level leakage power by spectral stochastic method.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Jacob Relles	An efficient decoupling capacitance optimization using piecewise polynomial models.	DATE	2009	DBLP BibTeX RDF
1	Zuying Luo, Jeffrey Fan, Sheldon X.-D. Tan	Localized Statistical 3D Thermal Analysis Considering Electro-Thermal Coupling.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Esteban Tlelo-Cuautle, Elyoenai Martínez-Romero, Carlos Sánchez-López, Sheldon X.-D. Tan	Symbolic formulation method for mixed-mode analog circuits using nullors.	ICECS	2009	DBLP DOI BibTeX RDF
1	Xiaoyi Wang, Yici Cai, Qiang Zhou, Sheldon X.-D. Tan, Thom Jefferson A. Eguia	Decoupling capacitance efficient placement for reducing transient power supply noise.	ICCAD	2009	DBLP BibTeX RDF
1	Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala	A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation.	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Le Kang, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Random Walk Guided Decap Embedding for Power/Ground Network Optimization.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Bruce McGaughy	Second-Order Balanced Truncation for Passive-Order Reduction of RLCK Circuits.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical Analysis of On-Chip Power Delivery Networks Considering Lognormal Leakage Current Variations With Spatial Correlation.	IEEE Trans. on Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Pu Liu, Sheldon X.-D. Tan, Boyuan Yan, Bruce McGaughy	An efficient terminal and model order reduction algorithm.	Integration	2008	DBLP DOI BibTeX RDF
1	Yici Cai, Jin Shi, Zhu Pan, Xianlong Hong, Sheldon X.-D. Tan	Large scale P/G grid transient simulation using hierarchical relaxed approach.	Integration	2008	DBLP DOI BibTeX RDF
1	Zuying Luo, Sheldon X.-D. Tan	Statistic Analysis of Power/Ground Networks Using Single-Node SOR Method.	ISQED	2008	DBLP DOI BibTeX RDF	SOR, Single node, Power/Ground Network, Algorithm, Statistic analysis
1	Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X.-D. Tan, Wenjian Yu, Jiarong Tong	Variational capacitance modeling using orthogonal polynomial method.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	random variable reduction, process variations, capacitance extraction, orthogonal decomposition
1	Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala	FEKIS: a fast architecture-level thermal analyzer for online thermal regulation.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	architecture, model reduction, thermal simulation
1	Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen 0005, Bruce McGaughy	DeMOR: decentralized model order reduction of linear networks with massive ports.	DAC	2008	DBLP DOI BibTeX RDF	multi-port networks, decentralized, model order reduction
1	Duo Li, Sheldon X.-D. Tan	Hierarchical Krylov subspace reduced order modeling of large RLC circuits.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Murli Tirumala	Architecture-level thermal behavioral characterization for multi-core microprocessors.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Bruce McGaughy	ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis.	DATE	2008	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu	Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace method.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala	Parameterized transient thermal behavioral modeling for chip multiprocessors.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Wei Wu, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	Efficient power modeling and software thermal sensing for runtime temperature monitoring.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Power, thermal
1	Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He	TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong	Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Bao Liu, Sheldon X.-D. Tan	Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite and Linear Programs.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Partitioning-based decoupling capacitor budgeting via sequence of linear programming.	Integration	2007	DBLP DOI BibTeX RDF
1	Ning Mi, Boyuan Yan, Sheldon X.-D. Tan, Jeffrey Fan, Hao Yu	General Block Structure-Preserving Reduced Order Modeling of Linear Dynamic Circuits.	ISQED	2007	DBLP DOI BibTeX RDF
1	Boyuan Yan, Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy	Passive Modeling of Interconnects by Waveform Shaping.	ISQED	2007	DBLP DOI BibTeX RDF
1	Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy	SBPOR: Second-Order Balanced Truncation for Passive Order Reduction of RLC Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan	Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach.	ASP-DAC	2007	DBLP DOI BibTeX RDF	programming method, decoupling capacitor budgeting algorithm, random walk approach, decap budgeting algorithm, power ground network design, isolation property, decap optimization process, leakage currents optimization algorithm, refined leakage model, heuristic method
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang	Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.	ASP-DAC	2007	DBLP DOI BibTeX RDF	stochastic parameterized model order reduction, Hermite polynomial chaos, stochastic model order reduction algorithm, stochastic Hermite polynomials, stochastic interconnect analysis, nonGaussian input variations, implicit system representation, block matrix structure, Monte Carlo methods, linear equations
1	Boyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy	Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor Form.	ASP-DAC	2007	DBLP DOI BibTeX RDF	moment-matching methods, passive interconnect macromodeling, descriptor form, passive model order reduction, projection-based truncated balanced realization method, large RLC interconnect circuits, Lur'e equation, algebraic Riccati equations, generalized Lyapunov equations, passivity preservation, congruence transformation, large scale interconnect circuit, linear systems, structure information, Krylov-subspace methods, block structure, balanced truncation
1	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Statistical model order reduction for interconnect circuits considering spatial correlations.	DATE	2007	DBLP DOI BibTeX RDF
1	Le Kang, Yici Cai, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan, Xiaoyi Wang	Simultaneous Switching Noise Consideration for Power/Ground Network Optimization.	CAD/Graphics	2007	DBLP DOI BibTeX RDF
1	Ning Mi, Sheldon X.-D. Tan, Pu Liu, Jian Cui, Yici Cai, Xianlong Hong	Stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lien Lu	Improving the reliability of on-chip data caches under process variations.	ICCD	2007	DBLP DOI BibTeX RDF
1	Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan	Voltage drop reduction for on-chip power delivery considering leakage current variations.	ICCD	2007	DBLP DOI BibTeX RDF
1	Zuying Luo, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong, Xiaoyi Wang, Zhu Pan, Jingjing Fu	Time-domain analysis methodology for large-scale RLC circuits and its applications.	Science in China Series F: Information Sciences	2006	DBLP DOI BibTeX RDF	RLC circuits, analog circuit analysis, P/G networks, algorithm complexity, time-domain analysis
1	Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002	Fast Thermal Simulation for Runtime Temperature Tracking and Management.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Hao Yu, Pu Liu, Sheldon X.-D. Tan, Lei He	Wideband passive multiport model order reduction and realization of RLCM circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Jeffrey Fan, I-Fan Liao, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong	Localized On-Chip Power Delivery Network Optimization via Sequence of Linear Programming.	ISQED	2006	DBLP DOI BibTeX RDF
1	Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu	Compact Reduced Order Modeling for Multiple-Port Interconnects.	ISQED	2006	DBLP DOI BibTeX RDF
1	Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan	SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Matching.	ISQED	2006	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong	High accurate pattern based precondition method for extremely large power/ground grid analysis.	ISPD	2006	DBLP DOI BibTeX RDF	pattern, iterative method, precondition, PCG
1	Andrew B. Kahng, Bao Liu, Sheldon X.-D. Tan	Efficient decoupling capacitor planning via convex programming methods.	ISPD	2006	DBLP DOI BibTeX RDF
1	Wei Wu, Lingling Jin, Jun Yang 0002, Pu Liu, Sheldon X.-D. Tan	A systematic method for functional unit power estimation in microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	microprocessor, power estimation, performance counter
1	Jin Shi, Yici Cai, Sheldon X.-D. Tan, Xianlong Hong	Efficient early stage resonance estimation techniques for C4 package.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan	Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation.	ICCD	2006	DBLP BibTeX RDF
1	Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan	A Fast Delay Computation for the Hybrid Structured Clock Network.	IEICE Transactions	2005	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan	A general hierarchical circuit modeling and simulation algorithm.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi	Hierarchical approach to exact symbolic analysis of large analog circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery.	ISQED	2005	DBLP DOI BibTeX RDF
1	Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan	Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
1	Jin Shi, Yici Cai, Xianlong Hong, Sheldon X.-D. Tan	Efficient Simulation of Power/Ground Networks with Package and Vias.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong	Partitioning-based approach to fast on-chip decap budgeting and minimization.	DAC	2005	DBLP DOI BibTeX RDF	on-chi, power/grid networks, simulation, optimization, IR drop, decoupling capacitor
1	Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan	A wideband hierarchical circuit reduction for massively coupled interconnects.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan	VLSI on-chip power/ground network optimization considering decap leakage currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Yici Cai, Zhu Pan, Sheldon X.-D. Tan, Xianlong Hong, Wenting Hou, Lifeng Wu	Relaxed hierarchical power/ground grid analysis.	ASP-DAC	2005	DBLP DOI BibTeX RDF

Publications of Sheldon X.-D. Tan Xiang-Dong Tan ( http://dblp.L3S.de/Authors/Sheldon_X.-D._Tan )