| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Kun-Hung Tsai, Shen-Iuan Liu |
A 104-GHz Phase-Locked Loop Using a VCO at Second Pole Frequency.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke-Hou Chen, Shen-Iuan Liu |
Inductorless Wideband CMOS Low-Noise Amplifiers Using Noise-Canceling Technique. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | I.-Ting Lee, Hung-Yu Lu, Shen-Iuan Liu |
A 6-GHz All-Digital Fractional-N Frequency Synthesizer Using FIR-Embedded Noise Filtering Technique. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | I.-Ting Lee, Shen-Iuan Liu |
G-Band Injection-Locked Frequency Dividers Using $\pi$-type LC Networks. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chieh Huang, Ping-Ying Wang, Shen-Iuan Liu |
An All-Digital Jitter Tolerance Measurement Technique for CDR Circuits. |
IEEE Trans. on Circuits and Systems |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen |
A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chieh Huang, Shen-Iuan Liu |
A 2.4GHz sub-harmonically injection-locked PLL with self-calibrated injection timing. |
ISSCC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo-Yu Lin, Shen-Iuan Liu |
Analysis and Design of D-Band Injection-Locked Frequency Dividers. |
J. Solid-State Circuits |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Yuan Kao, Shen-Iuan Liu |
A Digitally-Calibrated Phase-Locked Loop With Supply Sensitivity Suppression. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao-Ching Hung, Shen-Iuan Liu |
A Noise Filtering Technique for Fractional-N Frequency Synthesizers. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Jen Huang, Shigeisa Nagayasu, Shen-Iuan Liu |
A Rail-to-Rail Class-B Buffer With DC Level-Shifting Current Mirror and Distributed Miller Compensation for LCD Column Drivers. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao-Ching Hung, Shen-Iuan Liu |
A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Lin Hsieh, Shen-Iuan Liu |
Decision Feedback Equalizers Using the Back-Gate Feedback Technique. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo-Yu Lin, Shen-Iuan Liu |
A 132.6-GHz Phase-Locked Loop in 65 nm Digital CMOS. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chang-Lin Hsieh, Shen-Iuan Liu |
A 1-16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Ming Ying, Shen-Iuan Liu |
A 20Gb/s digitally adaptive equalizer/DFE with blind sampling. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Chieh Huang, Shen-Iuan Liu |
A 6Gb/s receiver with 32.7dB adaptive DFE-IIR equalization. |
ISSCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian-Hao Lu, Shen-Iuan Liu |
A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers. |
J. Solid-State Circuits |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jung-Yu Chang, Shen-Iuan Liu |
A Phase-Locked Loop With Background Leakage Current Compensation. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Yuan Kao, Shen-Iuan Liu |
A 1.62/2.7-Gb/s Adaptive Transmitter With Two-Tap Preemphasis Using a Propagation-Time Detector. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mu-Chen Huang, Shen-Iuan Liu |
A 10-MS/s-to-100-kS/s Power-Scalable Fully Differential CBSC 10-Bit Pipelined ADC With Adaptive Biasing. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Yuan Kao, Shen-Iuan Liu |
A 20-Gb/s Transmitter With Adaptive Preemphasis in 65-nm CMOS Technology. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu |
A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao-Ching Hung, Shen-Iuan Liu |
A Leakage-Compensated PLL in 65-nm CMOS Technology. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Mu-Chen Huang, Shen-Iuan Liu |
A Fully Differential Comparator-Based Switched-Capacitor DeltaSigma Modulator. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jung-Yu Chang, Che-Wei Fan, Che-Fu Liang, Shen-Iuan Liu |
A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | I.-Ting Lee, Kun-Hung Tsai, Shen-Iuan Liu |
A 104- to 112.8-GHz CMOS Injection-Locked Frequency Divider. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ming Lin, Shen-Iuan Liu, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu |
A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- muhboxm LTPS-TFT Technology. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian-Hao Lu, Shen-Iuan Liu |
A 50-Gb/s 10-mW Analog Equalizer Using Transformer Feedback Technique in 65-nm CMOS Technology. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Nan Chuang, Shen-Iuan Liu |
A 20-MHz to 3-GHz Wide-Range Multiphase Delay-Locked Loop. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | I.-Hsin Wang, Hwei-Yu Lee, Shen-Iuan Liu |
An 8-bit 20-MS/s ZCBC Time-Domain Analog-to-Digital Data Converter. |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jian-Hao Lu, Ke-Hou Chen, Shen-Iuan Liu |
Comments on "A 10-Gb/s Inductorless CMOS Analog Equalizer With an Interleaved Active Feedback Topology". |
IEEE Trans. on Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bo-Yu Lin, Kun-Hung Tsai, Shen-Iuan Liu |
A 128.24-to-137.00GHz injection-locked frequency divider in 65nm CMOS. |
ISSCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chao-Ching Hung, Shen-Iuan Liu |
A leakage-suppression technique for phase-locked systems in 65nm CMOS. |
ISSCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kun-Hung Tsai, Shen-Iuan Liu |
A 43.7mW 96GHz PLL in 65nm CMOS. |
ISSCC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Hwei-Yu Lee, Shen-Iuan Liu |
A 140MS/s 10-bit Pipelined ADC with a Folded S/H Stage. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Nan Chuang, Shen-Iuan Liu |
A 3-8 GHz Delay-Locked Loop With Cycle Jitter Calibration. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chihun Lee, Lan-Chou Cho, Jia-Hao Wu, Shen-Iuan Liu |
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Che-Fu Liang, Hong-Lin Chu, Shen-Iuan Liu |
10-Gb/s Inductorless CDRs With Digital Frequency Calibration. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Hung Lin, Shen-Iuan Liu |
Full-Rate Bang-Bang Phase/Frequency Detectors for Unilateral Continuous-Rate CDRs. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Ku Kao, Shen-Iuan Liu |
A Delay-Locked Loop With Statistical Background Calibration. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chuan-Kang Liang, Rong-Jyi Yang, Shen-Iuan Liu |
An All-Digital Fast-Locking Programmable DLL-Based Clock Generator. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | I.-Hsin Wang, Shen-Iuan Liu |
A 0.18-muhbox m CMOS 1.25-Gbps Automatic-Gain-Control Amplifier. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu |
A Multi-Band Burst-Mode Clock and Data Recovery Circuit. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hwei-Yu Lee, I.-Hsin Wang, Shen-Iuan Liu |
A 7-BIT 400MS/s sub-ranging flash ADC in 0.18um CMOS. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hwei-Yu Lee, Shen-Iuan Liu |
A 10-BIT 100MS/s pipelined ADC IN 0.18μm CMOS technology. |
SoCC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chi-Nan Chuang, Shen-Iuan Liu |
A 1 V Phase Locked Loop with Leakage Compensation in 0.13 µm CMOS Technology. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shao-Ku Kao, Shen-Iuan Liu |
All-Digital Clock Deskew Buffer with Variable Duty Cycles. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong-Jyi Yang, Shen-Iuan Liu |
A Wide-Range Multiphase Delay-Locked Loop Using Mixed-Mode VCDLs. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong-Jyi Yang, Shen-Iuan Liu |
A Fully Integrated 1.7-3.125 Gbps Clock and Data Recovery Circuit Using a Gated Frequency Detector. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chien-Hung Kuo, Chang-Hung Chen, Huang-Shih Lin, Shen-Iuan Liu |
A tunable bandpass /spl Delta//spl Sigma/ modulator using double sampling. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hua-Chin Lee, Chien-Chih Lin, Chia-Hsin Wu, Shen-Iuan Liu, Chorng-Kuang Wang, Hen-Wai Tsao |
A 15 mW 69 dB 2 Gsamples/s CMOS analog front-end for low-band UWB applications. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chia-Hsin Wu, Jieh-Wei Liao, Shen-Iuan Liu |
A 1V 4.2mW fully integrated 2.5Gb/s CMOS limiting amplifier using folded active inductors. |
ISCAS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu |
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Lee-An Ho, Shr-Lung Chen, Chien-Hung Kuo, Shen-Iuan Liu |
CMOS oversampling Sigma-Delta magnetic to digital converters. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
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