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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 29 occurrences of 19 keywords
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Results
Found 83 publication records. Showing 83 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto |
Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips.  |
IEICE Transactions  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Yuchun Ma, Satoshi Goto, Jason Cong |
Leakage-aware performance-driven TSV-planning based on network flow algorithm in 3D ICs. |
ISQED |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Satoshi Goto |
Voltage island-driven power optimization for application specific network-on-chip design. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tao Lin, Sheqin Dong, Song Chen, Satoshi Goto |
Linear optimal one-sided single-detour algorithm for untangling twisted bus. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto |
Buffer Planning for IP Placement Using Sliced-LFF. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong |
Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs. |
IEICE Transactions |
2011 |
DBLP BibTeX RDF |
|
| 1 | Tao Lin, Sheqin Dong, Song Chen, Yuchun Ma, Ou He, Satoshi Goto |
Novel and efficient min cut based voltage assignment in gate level. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto |
Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto |
Network flow-based simultaneous retiming and slack budgeting for low power design. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong |
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Xu He, Sheqin Dong, Yuchun Ma |
Signal through-the-silicon via planning and pin assignment for thermal and wire length optimization in 3D ICs. |
Integration |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wenxu Sheng, Sheqin Dong, Yuliang Wu, Satoshi Goto |
Fixed outline multi-bend bus driven floorplanning. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wentao Sui, Sheqin Dong, Jinian Bian |
Wirelength-driven force-directed 3D FPGA placement. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
SA, partition, placement, legalization, 3-D, force-directed |
| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
Bus via reduction based on floorplan revising. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
floorplan revising, via reduction, bus routing |
| 1 | Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto |
A revisit to voltage partitioning problem. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
quasiconvex assumption, voltage partition |
| 1 | Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto |
Floorplanning and topology generation for application-specific network-on-chip. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto |
Pipeline-Based Partition Exploration for Heterogeneous Multiprocessor Synthesis. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto |
Voltage and Level-Shifter Assignment Driven Floorplanning. |
IEICE Transactions |
2009 |
DBLP BibTeX RDF |
|
| 1 | Xu He, Sheqin Dong, Yuchun Ma, Xianlong Hong |
Simultaneous buffer and interlayer via planning for 3D floorplanning. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Bei Yu, Sheqin Dong, Satoshi Goto, Song Chen |
Voltage-island driven floorplanning considering level-shifter positions. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
convex network flow, level shifter assignment, voltage assignment, white space redistribution, voltage-island |
| 1 | Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto |
Integrated interlayer via planning and pin assignment for 3D ICs. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Hongjie Bai, Xianlong Hong, Satoshi Goto |
Buffer Planning for 3D ICs. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto |
Fast Custom Instruction Identification Algorithm Based on Basic Convex Pattern Model for Supporting ASIP Automated Design. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto |
Exploring Partitions Based on Search Space Smoothing for Heterogeneous Multiprocessor System. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto |
Automated Specific Instruction Customization Methodology for Multimedia Processor Acceleration. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Chenqian Jiang, Sheqin Dong, Satoshi Goto |
Cache miss reduction through hardware-assisted loop optimization. |
CSCWD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong, Yang Song, Satoshi Goto |
HyMacs: hybrid memory access optimization based on custom-instruction scheduling. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
asip, cad algorithm, hardware/software co-design |
| 1 | Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong |
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto |
Symmetry constraint based on mismatch analysis for analog layout in SOI technology. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng |
A novel fixed-outline floorplanner with zero deadspace for hierarchical design. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
floorplanner, soft modules, zero deadspace, fixed-outline |
| 1 | Yaoguang Wei, Sheqin Dong, Xianlong Hong |
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement. |
Integration |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongjie Bai, Sheqin Dong, Xianlong Hong |
Congestion Driven Buffer Planning for X-Architecture. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Liu Yang, Sheqin Dong, Yuchun Ma, Xianlong Hong |
Interconnect Power Optimization Based on Timing Analysis. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong |
A Fast Custom Instructions Identification Algorithm based on Basic Convex Pattern Model for Supporting ASIP Automated Design. |
CSCWD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong |
An effective buffer planning algorithm for IP based fixed-outline SOC placement. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
buffer planning, very large scale integration (VLSI), floorplanning, fixed-outline |
| 1 | Yaoguang Wei, Sheqin Dong, Xianlong Hong, Yuchun Ma |
An accurate and efficient probabilistic congestion estimation model in x architecture. |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
congestion estimation, dynamic resource assignment, the X architecture, routability |
| 1 | Yuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou |
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
graph-based approach, microarchitecture pipelining optimization, throughput-aware floorplanning, block pipelining, interconnect pipelining, graph-based algorithm, mixed integer linear programming, wire pipelining |
| 1 | Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong |
Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
thermal-optimal placement, thermal-driven symmetry constraint, analog layout, thermal constraint, hot-spot effect, temperature gradient, symmetrical devices, placement process, geometric symmetry, corner block list, thermal model |
| 1 | Lingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
A Fast 3D-BSG Algorithm for 3D Packing Problem. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
General Floorplans with L/T-Shaped Blocks Using Corner Block List. |
J. Comput. Sci. Technol. |
2006 |
DBLP DOI BibTeX RDF |
corner block list, L/T-shaped blocks, floorplanning |
| 1 | Di Long, Xianlong Hong, Sheqin Dong |
Signal-path driven partition and placement for analog circuit. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
analog placement, device merging, layout automation, signal-path, symmetry constrain, circuit partition |
| 1 | Liu Yang, Sheqin Dong, Xianlong Hong, Yuchun Ma |
A Two-stage Incremental Floorplanning Algorithm with Boundary Constraints. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Shuyi Zheng, Xianlong Hong |
Floorplanning for 2.5-D system integration using multi-layer-BSG structure. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaojun Wei, Sheqin Dong, Xianlong Hong, Youliang Wu |
On handling the fixed-outline constraints of floorplanning using less flexibility first principles. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
Buffer planning based on block exchanging. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong |
Stochastic Local Search Using the Search Space Smoothing Meta-Heuristic: A Case Study. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Fan Guo, Jun Yuan, Rensheng Wang, Xianlong Hong |
A Novel Tour Construction Heuristic for Traveling Salesman Problem Using LFF Principle. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kang Zhao, Jinian Bian, Sheqin Dong |
A Heterogeneous Dependency Graph as Intermediate Representation for Instruction Set Customization. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Rensheng Wang, Fan Guo, Jun Yuan, Xianlong Hong |
Floorplanning by A Revised 3-D Corner Block List with sub-C+-tree. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng, Jun Gu |
Buffer planning as an Integral part of floorplanning with consideration of routing congestion. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng |
Buffer Planning Algorithm Based on Partial Clustered Floorplanning. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong Liu, Sheqin Dong, Xianlong Hong |
Fixed-outline floorplanning based on common subsequence. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
common subsequence, floorplanning, fixed-outline |
| 1 | Renshen Wang, Sheqin Dong, Xianlong Hong |
An improved P-admissible floorplan representation based on Corner Block List. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jun Yuan, Sheqin Dong, Xianlong Hong, Yuliang Wu |
LFF algorithm for heterogeneous FPGA floorplanning. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng |
VLSI block placement with alignment constraints based on corner block list. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Chung-Kuan Cheng |
Performance constrained floorplanning based on partial clustering [IC layout]. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhe Zhou, Sheqin Dong, Xianlong Hong, Yuliang Wu, Yoji Kajitani |
A new approach based on LFF for optimization of dynamic hardware reconfigurations. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong Liu, Sheqin Dong, Xianlong Hong, Yoji Kajitani |
Fixed-outline floorplanning with constraints through instance augmentation. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Di Long, Xianlong Hong, Sheqin Dong |
Optimal two-dimension common centroid layout generation for MOS transistors unit-circuit. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hongjie Bai, Sheqin Dong, Xianlong Hong, Song Chen |
A New Buffer Planning Algorithm Based on Room Resizing. |
EUC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Rong Liu, Sheqin Dong, Xianlong Hong |
An efficient algorithm to fixed-outline floorplanning based on instance augmentation. |
CAD/Graphics |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Stairway compaction using corner block list and its applications with rectilinear blocks. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
corner block list, rectilinear blocks, Floorplanning |
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
A buffer planning algorithm for chip-level floorplanning. |
Science in China Series F: Information Sciences |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Xianlong Hong, Yuchun Ma, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Corner block list representation and its application with boundary constraints. |
Science in China Series F: Information Sciences |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Chung-Kuan Cheng, Jun Gu |
Fast Evaluation of Bounded Slice-Line Grid. |
J. Comput. Sci. Technol. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
A buffer planning algorithm with congestion optimization. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Buffer allocation algorithm with consideration of routing congestion. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Zhong Yang, Xianlong Hong, Yuliang Wu |
Module placement based on quadratic programming and rectangle packing using less flexibility first principle. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Sheqin Dong, Xianlong Hong, Yuliang Wu, Jun Gu |
Deterministic VLSI Block Placement Algorithm Using Less Flexibility First Principle. |
J. Comput. Sci. Technol. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
An integrated floorplanning with an efficient buffer planning algorithm. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
floorplanning, buffer insertion, routability |
| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Song Chen, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Dynamic global buffer planning optimization based on detail block locating and congestion analysis. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
congestion, floorplanning, buffer insertion, routability |
| 1 | Rui Liu, Sheqin Dong, Xianlong Hong, Di Long, Jun Gu |
Algorithms for analog VLSI 2D stack generation and block merging. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Song Chen, Xianlong Hong, Sheqin Dong, Yuchun Ma, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Evaluating a bounded slice-line grid assignment in O(nlogn) time. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Song Chen, Chung-Kuan Cheng, Jun Gu |
Arbitrary convex and concave rectilinear block packing based on corner block list. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
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| 1 | Sheqin Dong, Shuo Zhou, Xianlong Hong, Chung-Kuan Cheng, Jun Gu, Yici Cai |
An Optimum Placement Search Algorithm Based on Extended Corner Block List. |
J. Comput. Sci. Technol. |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
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| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Floorplanning with abutment constraints based on corner block list. |
Integration |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Shuo Zhou, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
ECBL: an extended corner block list with solution space including optimum placement. |
ISPD |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu |
VLSI block placement using less flexibility first principles. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu |
VLSI floorplanning with boundary constraints based on corner block list. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
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| 1 | Xianlong Hong, Gang Huang, Yici Cai, Jiangchun Gu, Sheqin Dong, Chung-Kuan Cheng, Jun Gu |
Corner Block List: An Effective and Efficient Topological Representation of Non-Slicing Floorplan. |
ICCAD |
2000 |
DBLP BibTeX RDF |
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