| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang |
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.  |
ACM Trans. Design Autom. Electr. Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Chao Lee, Yiyu Shi, Yu-Guang Chen, Diana Marculescu, Shih-Chieh Chang |
Efficient on-line module-level wake-up scheduling for high performance multi-module designs. |
ISPD |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Mac Y. C. Kao, Kun-Ting Tsai, Hsuan-Ming Chou, Shih-Chieh Chang |
Post silicon skew tuning: Survey and analysis. |
ASP-DAC |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang, Wing-Kai Hon |
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units. |
INFOCOM |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Chiang Wu, Ming-Chao Lee, Diana Marculescu, Shih-Chieh Chang |
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Hsiu-Yi Lin, Chun-Yao Wang, Shih-Chieh Chang, Yung-Chih Chen, Hsuan-Ming Chou, Ching-Yi Huang, Yen-Chi Yang, Chun-Chien Shen |
A probabilistic analysis method for functional qualification under Mutation Analysis. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Performance Optimization Using Variable-Latency Design Style. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Shih-Chieh Chang |
Efficient Pattern Matching Algorithm for Memory Architecture. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kai-Chiang Wu, Diana Marculescu, Ming-Chao Lee, Shih-Chieh Chang |
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits. |
ISLPED |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chiao-Ling Lung, Yu-Shih Su, Shih-Hsiu Huang, Yiyu Shi, Shih-Chieh Chang |
Fault-tolerant 3D clock network. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Chao Lee, Yu-Guang Chen, Ding-Kei Huang, Shih-Chieh Chang |
NBTI-aware power gating design. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Chen-Hsiung Liu, Shih-Chieh Chang |
Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU. |
GLOBECOM |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiao-Ling Lung, Yi-Lun Ho, Ding-Ming Kwai, Shih-Chieh Chang |
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Hsuan-Ming Chou, Hao Yu, Shih-Chieh Chang |
Useful-skew clock optimization for multi-power mode designs. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mac Y. C. Kao, Kun-Ting Tsai, Shih-Chieh Chang |
A robust architecture for post-silicon skew tuning. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang |
On the preconditioner of conjugate gradient method - A power grid simulation perspective. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | De-Shiuan Chiou, Yu-Ting Chen, Da-Cheng Juan, Shih-Chieh Chang |
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang |
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang |
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang |
An efficient phase detector connection structure for the skew synchronization system. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
adjustable delay buffer, phase detector, post-silicon tuning |
| 1 | Cheng-Hung Lin, Sheng-Yu Tsai, Chen-Hsiung Liu, Shih-Chieh Chang, Jyuo-Min Shyu |
Accelerating String Matching Using Multi-Threaded Algorithm on GPU. |
GLOBECOM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang |
Clock skew optimization considering complicated power modes. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Yu-Chien Kao, Hsuan-Ming Chou, Kun-Ting Tsai, Shih-Chieh Chang |
Synthesis of an efficient controlling structure for post-silicon clock skew minimization. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang |
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Spare Cells With Constant Insertion for Engineering Change. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang |
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Ming-Chao Lee, Yu-Ting Chen, Yo-Tzu Cheng, Shih-Chieh Chang |
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yu-Shih Su, Wing-Kai Hon, Cheng-Chih Yang, Shih-Chieh Chang, Yeong-Jar Chang |
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. |
ICCAD |
2009 |
DBLP BibTeX RDF |
|
| 1 | Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang |
Synthesis of a novel timing-error detection architecture. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
fault tolerance, Logic synthesis |
| 1 | Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang |
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang |
A novel sequential circuit optimization with clock gating logic. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Timing analysis considering IR drop waveforms in power gating designs. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang |
Optimization of Pattern Matching Circuits for Regular Expression on FPGA. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang |
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Cheng-Hung Lin, Chun-Yao Wang, Shih-Chieh Chang, Pei-Hsin Ho |
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aida Todri, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Electromigration and voltage drop aware power grid optimization for power gated ICs. |
ISLPED |
2007 |
DBLP DOI BibTeX RDF |
power supply grid, power gating, electromigration |
| 1 | Cheng-Hung Lin, Yu-Tang Tai, Shih-Chieh Chang |
Optimization of pattern matching algorithm for memory based architecture. |
ANCS |
2007 |
DBLP DOI BibTeX RDF |
intrusion detection, pattern matching, DFA |
| 1 | Yu-Shih Su, Da-Chung Wang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih-Chieh Chang |
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang |
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang |
Analysis and optimization of power-gated ICs with multiple power gating configurations. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Ya-Ting Chang, Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Engineering change using spare cells with constant insertion. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhong-Zhen Wu, Shih-Chieh Chang |
Multiple wire reconnections based on implication flow graph. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
global flow optimization (GFO), implication flow graph (IFG), mandatory assignment, multiple wire reconnection, redundant wire, Automatic test pattern generation (ATPG) |
| 1 | Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh |
Power minimization for dynamic PLAs. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Le Huang, Chun-Yao Wang, Richard Yeh, Shih-Chieh Chang, Yung-Chih Chen |
Language-Based High Level Transaction Extraction on On-chip Buses. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang, Chingwei Yeh |
Timing driven power gating. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
leakage current, power gating, IR drop |
| 1 | Kai-Chiang Wu, Cheng-Tao Hsieh, Shih-Chieh Chang |
Delay variation tolerance for domino circuits. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Chih-Tsun Huang, Chang-Ping Jiang, Shih-Chieh Chang |
Optimization of regular expression pattern matching circuits on FPGA. |
DATE Designers' Forum |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Min Kuo, Yue-Lung Chang, Shih-Chieh Chang |
Efficient Boolean characteristic function for fast timed ATPG. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Yen-Fong Lee, Shi-Yu Huang, Sheng-Yu Hsu, I-Ling Chen, Cheng-Tao Shieh, Jian-Cheng Lin, Shih-Chieh Chang |
Power estimation starategies for a low-power security processor. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Tzyy-Kuen Tien, Chih-Shen Tsai, Shih-Chieh Chang, Chingwei Yeh |
Power minimization for dynamic PLAs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone |
Design and design automation of rectification logic for engineering change. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang |
FPGA technology mapping optimization by rewiring algorithms. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang |
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. |
Asian Test Symposium |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Cheng-Tao Hsieh, Kai-Chiang Wu |
Re-synthesis for delay variation tolerance. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
tolerance, delay variation |
| 1 | Cheng-Tao Hsieh, Jian-Cheng Lin, Shih-Chieh Chang |
A vectorless estimation of maximum instantaneous current for sequential circuits. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh |
Embedded core test generation using broadcast test architecture and netlist scrambling. |
IEEE Transactions on Reliability |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Tzyy-Kuen Tien, Shih-Chieh Chang, Tong-Kai Tsai |
Crosstalk alleviation for dynamic PLAs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang |
Crosstalk Alleviation for Dynamic PLAs. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jiann-Chyi Rau, Y. M. Chen, Shih-Chieh Chang |
A don't-care based image circuit for function verification. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Jiann-Chyi Rau |
A timing-driven pseudoexhaustive testing for VLSI circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Zhong-Zhen Wu |
Theorems and extensions of single wire replacement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang |
Charge-sharing alleviation and detection for CMOS domino circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone |
Embedded Core Testing Using Broadcast Test Architecture. (PDF / PS) |
DFT |
2001 |
DBLP DOI BibTeX RDF |
test pattern broadcasting, data decryption, IEEE P1500 standard, data encryption, core-based testing |
| 1 | Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang |
TAIR: testability analysis by implication reasoning. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Yin-He Su, Ching-Hwa Cheng, Shih-Chieh Chang |
Novel techniques for improving testability analysis. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
closed-form formulation, implication reasoning, TAIR, tree-structured circuit, logic testing, logic testing, controllability, controllability, built-in self test, automatic test pattern generation, BIST, observability, observability, stuck-at fault, shift registers, testability analysis, test patterns |
| 1 | Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang |
Charge sharing fault analysis and testing for CMOS domino logic circuits. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors |
| 1 | Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone |
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits. (PDF / PS) |
DFT |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang |
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Zhong-Zhen Wu, He-Zhe Yu |
Wire Reconnections Based on Implication Flow Graph. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska |
Circuit Optimization by Rewiring. |
IEEE Trans. Computers |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, David Ihsin Cheng |
Efficient Boolean division and substitution using redundancy addition and removing. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
Power reduction through iterative gate sizing and voltage scaling. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone |
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. (PDF / PS) |
DFT |
1999 |
DBLP DOI BibTeX RDF |
charge sharing, cs-vulnerability, pseudo gate, ATPG, domino circuit |
| 1 | Shih-Chieh Chang, Jung-Cheng Chuang, Zhong-Zhen Wu |
Synthesis for multiple input wires replacement of a gate for wiring consideration. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu |
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai |
A novel combinational testability analysis by considering signal correlation. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, David Ihsin Cheng |
Efficient Boolean Division and Substitution. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins |
| 1 | Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska |
Postlayout logic restructuring using alternative wires. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng |
Perturb and simplify: multilevel Boolean network optimizer. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang |
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Lukas P. P. P. van Ginneken, Malgorzata Marek-Sadowska |
Fast Boolean optimization by rewiring. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Boolean logic optimization, boolean optimization, mandatory assignments, Automatic Test Pattern Generation, automatic testing, rewiring |
| 1 | Chih-Chang Lin, Kuang-Chien Chen, Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng |
Logic Synthesis for Engineering Change. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng |
An Efficient Algorithm for Local Don't Care Sets Calculation. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, David Ihsin Cheng, Malgorzata Marek-Sadowska |
Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions. |
EDAC-ETC-EUROASIC |
1994 |
DBLP BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Kwang-Ting Cheng, Nam Sung Woo, Malgorzata Marek-Sadowska |
Layout Driven Logic Synthesis for FPGAs. |
DAC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Perturb and simplify: multi-level boolean network optimizer. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Chieh Chang, Malgorzata Marek-Sadowska |
Technology Mapping via Transformations of Function Graphs. |
ICCD |
1992 |
DBLP BibTeX RDF |
|
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