| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng |
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.  |
ASP-DAC  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Guan-Yu Jhuo, Wei-Lun Huang |
Minimum Inserted Buffers for Clock Period Minimization. |
J. Inf. Sci. Eng. |
2011 |
DBLP BibTeX RDF |
|
| 1 | Chih-Hung Lee, Shih-Hsu Huang, Chun-Hua Cheng |
Accurate TSV Number Minimization in High-Level Synthesis. |
J. Inf. Sci. Eng. |
2011 |
DBLP BibTeX RDF |
|
| 1 | Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang |
TSV sharing through multiplexing for TSV count minimization in high-level synthesis. |
SoCC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Resource Selection and Binding of Nonzero Clock Skew Circuits for Standby Leakage Current Minimization. |
J. Inf. Sci. Eng. |
2010 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan |
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating. |
ASP-DAC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
Opposite-phase register switching for peak current minimization. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
peak current, sequential circuit synthesis, Logic synthesis, IC testing |
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Minimum-Period Register Binding. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Da-Chen Tzeng |
Simultaneous Clock Skew Scheduling and Power-Gated Module Selection for Standby Leakage Minimization. |
J. Inf. Sci. Eng. |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Song-Bin Pan |
Synthesis of Anti-Aging Gated Clock Designs. |
J. Inf. Sci. Eng. |
2009 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Timing driven power gating in high-level synthesis. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jheng-Fu Yeh, Chun-Hua Cheng, Shih-Hsu Huang |
Surge Current Minimization in High-level Synthesis. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Power-Management Scheduling for Peak Power Minimization. |
J. Inf. Sci. Eng. |
2008 |
DBLP BibTeX RDF |
|
| 1 | Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu |
Type-matching clock tree for zero skew clock gating. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
physical design, gated clock, clock network synthesis |
| 1 | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
Opposite-Phase Clock Tree for Peak Current Reduction. |
IEICE Transactions |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yow-Tyng Nieh |
Clock skew scheduling with race conditions considered. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
Sequential circuits, logic synthesis, performance optimization, timing optimization |
| 1 | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
A Fast Register Scheduling Approach to the Architecture of Multiple Clocking Domains. |
J. Inf. Sci. Eng. |
2007 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chia-Ming Chang, Yow-Tyng Nieh |
Clock Period Minimization with Minimum Delay Insertion. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei-Ting Yen, Shih-Hsu Huang, Chun-Hua Cheng |
Simultaneous Operation Scheduling and Operation Delay Selection to Minimize Cycle-by-Cycle Power Differential. |
EUC Workshops |
2007 |
DBLP DOI BibTeX RDF |
Cycle-by-cycle Power Differential, Low Power, High-Level Synthesis, Integer Linear Programming, Operation Scheduling, Data-Path Synthesis |
| 1 | Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang |
A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. |
EUC |
2007 |
DBLP DOI BibTeX RDF |
Reused Block, Modeling, Power Consumption, Voltage Drop |
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
An ILP Approach to the Slack Driven Scheduling Problem. |
IEICE Transactions |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yow-Tyng Nieh |
Synthesis of nonzero clock skew circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Yow-Tyng Nieh, Wei-Chieh Yu |
Register binding for clock period minimization. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
high-level synthesis, clock skew, timing optimization |
| 1 | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
Fast multi-domain clock skew scheduling for peak current reduction. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang |
Peak Power Minimization through Power Management Scheduling. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
Operation Scheduling for False Loop Free Circuits. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chun-Hua Cheng, Chung-Hsin Chiang, Chia-Ming Chang |
An ILP Approach to the Simultaneous Application of Operation Scheduling and Power Management. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Shi-Zhi Liu, Yi-Rung Chen, Jian-Yuan Lai |
High-Speed Fuzzy Inference Processor Using Active Rules Identification. |
JCIS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh |
State re-encoding for peak current minimization. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
peak current, sequential circuit synthesis, finite state machine |
| 1 | Shih-Hsu Huang, Jian-Yuan Lai |
A High Speed Fuzzy Inference Processor with Dynamic Analysis and Scheduling Capabilities. |
IEICE Transactions |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chung-Hsin Chiang, Chun-Hua Cheng |
Three-dimension scheduling under multi-cycle interconnect communications. |
IEICE Electronic Express |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Jian-Yuan Lai |
High-Speed VLSI Fuzzy Inference Processor for Trapezoid-Shaped Membership Functions. |
J. Inf. Sci. Eng. |
2005 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu |
Race-condition-aware clock skew scheduling. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
sequential circuits, high performance, timing optimization |
| 1 | Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu |
Minimizing peak current via opposite-phase clock tree. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
low power, physical design, clock network synthesis |
| 1 | Shih-Hsu Huang, Chun-Hua Cheng |
A formal approach to the slack driven scheduling problem in high-level synthesis. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chih-Hung Lee, Chin-Hung Su, Shih-Hsu Huang, Chih-Yuan Lin, Tsai-Ming Hsieh |
Floorplanning with clock tree estimation. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yi-Rung Chen |
VLSI implementation of type-2 fuzzy inference processor. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yi-Siang Hsu, Chiu-Cheng Lin |
A Timing Driven Crosstalk Optimizer for Gridded Channel Routing. |
IEICE Transactions |
2004 |
DBLP BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yow-Tyng Nieh |
Clock Period Minimization of Non-Zero Clock Skew Circuits. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Wen-Hon Peng, Jian-Yuan Lai |
Automatic synthesis of fuzzy systems based on trapezoid-shaped membership functions. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yi-Siang Hsu |
A timing driven approach for crosstalk minimization in gridded channel routing. |
APCCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Chu-Liao Wang |
An effective floorplan-based power distribution network design methodology under reliability constraints. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang |
An effective low power design methodology based on interconnect prediction. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Jian-Yuan Lai |
A High Speed VLSI Fuzzy Logic Controller With Pipeline Architecture. |
FUZZ-IEEE |
2001 |
DBLP BibTeX RDF |
|
| 1 | Mely Chen Chi, Shih-Hsu Huang |
A Reliable Clock Tree Design Methodology for ASIC Designs. |
ISQED |
2000 |
DBLP DOI BibTeX RDF |
Clock tree design, Clock tree synthesis |
| 1 | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang |
A new approach to schedule operations across nested-ifs and nested-loops. |
Microprocessing and Microprogramming |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Yu-Chin Hsu, Yen-Jen Oyang |
A new scheduling algorithm for synthesizing the control blocks of control-dominated circuits. |
Microprocessing and Microprogramming |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang |
Synthesis of false loop free circuits. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Shih-Hsu Huang, Cheng-Tsung Hwang, Yu-Chin Hsu, Yen-Jen Oyang |
A new approach to schedule operations across nested-ifs and nested-loops. |
MICRO |
1992 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")