Search results for "Shih-Lien Lu"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky	Design for test and reliability in ultimate CMOS.	DATE	2012	DBLP BibTeX RDF
1	Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu	Adaptive Cache Design to Enable Reliable Low-Voltage Operation.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De	A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De	Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays.	J. Solid-State Circuits	2011	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu	Automatic Pipelining From Transactional Datapath Specifications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De	All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control.	IEEE Trans. on Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu	Energy-efficient cache design using variable-strength error-correcting codes.	ISCA	2011	DBLP DOI BibTeX RDF
1	Ilya Wagner, Shih-Lien Lu	Distributed hardware matcher framework for SoC survivability.	DATE	2011	DBLP BibTeX RDF
1	Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu	Reducing cache power with low-cost, multi-bit error-correcting codes.	ISCA	2010	DBLP DOI BibTeX RDF	ecc, edram, idle power, idle states, multi-bit ecc, refresh power, vccmin, dram
1	Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	Resilient microprocessor design for high performance & energy efficiency.	ISLPED	2010	DBLP DOI BibTeX RDF	resilient design
1	Keith A. Bowman, Carlos Tokunaga, James Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De	Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency.	CICC	2010	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam	Automatic multithreaded pipeline synthesis from transactional datapath specifications.	DAC	2010	DBLP DOI BibTeX RDF	automatic pipelining, datapath specification, design exploration of x86 processor pipelines, multithreading, hardware synthesis
1	Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah	PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction.	ISSCC	2010	DBLP DOI BibTeX RDF
1	James Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De	A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance.	ISSCC	2010	DBLP DOI BibTeX RDF
1	James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De	Resilient design in scaled CMOS for energy efficiency.	ASP-DAC	2010	DBLP DOI BibTeX RDF
1	Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu	Automatic pipelining from transactional datapath specifications.	DATE	2010	DBLP BibTeX RDF
1	Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu	Trading Off Cache Capacity for Low-Voltage Operation.	IEEE Micro	2009	DBLP DOI BibTeX RDF
1	Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh	Low power adaptive pipeline based on instruction isolation.	ISQED	2009	DBLP DOI BibTeX RDF
1	Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu	Improving cache lifetime reliability at ultra-low voltages.	MICRO	2009	DBLP DOI BibTeX RDF
1	Keith A. Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar	Circuit techniques for dynamic variation tolerance.	DAC	2009	DBLP DOI BibTeX RDF	dynamic variations, error-detection sequential, replica paths, resilient circuits, variation sensors, variation-tolerant circuits, error detection, error correction, error recovery, parameter variations, timing errors
1	Ataur R. Patwary, Bibiche M. Geuskens, Shih-Lien Lu	Content Addressable Memory for Low-Power and High-Performance Applications.	CSIE	2009	DBLP DOI BibTeX RDF
1	James Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik	Resilient circuits - Enabling energy-efficient performance and reliability.	ICCAD	2009	DBLP BibTeX RDF
1	Eriko Nurvitadhi, Jumnit Hong, Shih-Lien Lu	Active Cache Emulator.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Shih-Lien Lu, Peter Yiannacouras, Taeweon Suh, Rolf Kassa, Michael Konow	A Desktop Computer with a Reconfigurable Pentium®.	TRETS	2008	DBLP DOI BibTeX RDF	Pentium®, simulator, model, FPGA, architecture, operating system, reconfigurable, emulator, exploration, accelerator, processor
1	Shih-Lien Lu, Ravichandran Ramachandran	Carry Logic.	Wiley Encyclopedia of Computer Science and Engineering	2008	DBLP DOI BibTeX RDF
1	Changjian Gao, Shih-Lien Lu	Novel FPGA based Haar classifier face detection algorithm acceleration.	FPL	2008	DBLP DOI BibTeX RDF
1	Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu	Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.	ISCA	2008	DBLP DOI BibTeX RDF
1	John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic	RAMP: Research Accelerator for Multiple Processors.	IEEE Micro	2007	DBLP DOI BibTeX RDF	field-programmable gate arrays, distributed systems, integration, parallel architectures, transactional memory, emulation, distributed-shared memory, hardware-software codesign, modeling of computer architecture
1	Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy	Fine-Grained Redundancy in Adders.	ISQED	2007	DBLP DOI BibTeX RDF
1	Taeweon Suh, Shih-Lien Lu, Hsien-Hsin S. Lee	An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems.	FPL	2007	DBLP DOI BibTeX RDF
1	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
1	Wei Wu, Sheldon X.-D. Tan, Jun Yang 0002, Shih-Lien Lu	Improving the reliability of on-chip data caches under process variations.	ICCD	2007	DBLP DOI BibTeX RDF
1	Jumnit Hong, Eriko Nurvitadhi, Shih-Lien Lu	Design, implementation, and verification of active cache emulator (ACE).	FPGA	2006	DBLP DOI BibTeX RDF	FPGA-based emulator, real-time emulation, cache modeling
1	Chunrong Lai, Shih-Lien Lu, Yurong Chen, Trista Chen	Improving branch prediction accuracy with parallel conservative correctors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	confidence mechanism, branch prediction, corrector
1	Eriko Nurvitadhi, Nirut Chalainanont, Shih-Lien Lu	Characterization of L3 cache behavior of SPECjAppServer2002 and TPC-C.	ICS	2005	DBLP DOI BibTeX RDF	L3 characterization, application server and OLTP, emulator
1	Shih-Lien Lu	Speeding Up Processing with Approximation Circuits.	IEEE Computer	2004	DBLP DOI BibTeX RDF
1	Chunrong Lai, Shih-Lien Lu	Efficient Victim Mechanism on Sector Cache Organization.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
1	Shih-Lien Lu, Konrad Lai	Implementation of HW$im - A Real-Time Configurable Cache Simulator.	FPL	2003	DBLP DOI BibTeX RDF
1	Shih-Chang Lai, Shih-Lien Lu	Hardware-based Pointer Data Prefetcher.	ICCD	2003	DBLP DOI BibTeX RDF
1	Shih-Chang Lai, Shih-Lien Lu, Jih-Kwon Peir	Ditto Processor.	DSN	2002	DBLP DOI BibTeX RDF
1	Steven Hsu, Shih-Lien Lu, Shih-Chang Lai, Ram Krishnamurthy, Konrad Lai	Dynamic addressing memory arrays with physical locality.	MICRO	2002	DBLP DOI BibTeX RDF
1	Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai	Bloom filtering cache misses for accurate data speculation and prefetching.	ICS	2002	DBLP DOI BibTeX RDF	bloom filter, instruction scheduling, data cache, data prefetching, data speculation
1	Tong Liu, Shih-Lien Lu	Performance improvement with circuit-level speculation.	MICRO	2000	DBLP DOI BibTeX RDF
1	Michael F. Miller, Kenneth J. Janik, Shih-Lien Lu	Non-Stalling CounterFlow Architecture.	HPCA	1998	DBLP DOI BibTeX RDF
1	Kenneth J. Janik, Shih-Lien Lu, Michael F. Miller	Advances of the Counterflow Pipeline Microarchitecture.	HPCA	1997	DBLP DOI BibTeX RDF	counterflow, CFPP, virtual register, architecture, pipeline, dataflow, VRP
1	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Shih-Lien Lu	Implementation of micropipelines in enable/disable CMOS differential logic.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Chih-Ming Chang, Shih-Lien Lu	Design of a static MIMD data flow processor using micropipelines.	IEEE Trans. VLSI Syst.	1995	DBLP DOI BibTeX RDF
1	Chung-Ping Wan, Bing J. Sheu, Shih-Lien Lu	Device and circuit simulation interface for an integrated VLSI design environment.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF

Publications of "Shih-Lien Lu" ( http://dblp.L3S.de/Authors/Shih-Lien_Lu )