Search results for "Shinobu Fujita"

Found 13 publication records. Showing 13 according to the selection in the facets

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini	Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Shinobu Fujita, Shinichi Yasuda, Dae Sung Lee, Xiangyu Chen, Deji Akinwande, H.-S. Philip Wong	Detachable nano-carbon chip with ultra low power.	DAC	2010	DBLP DOI BibTeX RDF	NEMS, ultra-low power, 3D-IC
1	Shinichi Yasuda, Tetsufumi Tanamoto, Kazutaka Ikegami, Atsuhiro Kinoshita, Keiko Abe, Hirotaka Nishino, Shinobu Fujita	High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	dopant-segregated schottky transistor, nonvolatile configurable memory
1	Kumiko Nomura, Keiko Abe, Shinobu Fujita, Yasuhiko Kurosawa, Atsushi Kageshima	Performance analysis of 3D-IC for multi-core processors in sub-65nm CMOS technologies.	ISCAS	2010	DBLP DOI BibTeX RDF
1	Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger	CMOS vs Nano: comrades or rivals?	FPGA	2009	DBLP DOI BibTeX RDF	fpga, nanotechnology
1	Shinobu Fujita	Nano-electronics challenge chip designers meet real nano-electronics in 2010s?	DATE	2009	DBLP BibTeX RDF
1	Shinobu Fujita, Keiko Abe, Kumiko Nomura, Shinichi Yasuda, Tetsufumi Tanamoto	Perspectives and Issues in 3D-IC from Designers' Point of View.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Bipul Chandra Paul, Shinobu Fujita, Masaki Okajima	ROM based logic (RBL) design: High-performance and low-power adders.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	JETC	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
1	Toshio Mochizuki, Hiroshi Kato, Kazaru Yaegashi, Toshihisa Nishimori, Yusuke Nagamori, Shinobu Fujita	ProBoPortable: does the cellular phone software promote emergent division of labor in project-based learning?	CSCL	2007	DBLP BibTeX RDF
1	Ryuji Ohba, Daisuke Matsushita, Koichi Muraoka, Shinichi Yasuda, Tetsufumi Tanamoto, Ken Uchida, Shinobu Fujita	Si Nanocrystal MOSFET with Silicon Nitride Tunnel Insulator for High-rate Random Number Generation.	ISVLSI	2006	DBLP DOI BibTeX RDF
1	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Modeling and analysis of circuit performance of ballistic CNFET.	DAC	2006	DBLP DOI BibTeX RDF	ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, circuit performance

Publications of "Shinobu Fujita" ( http://dblp.L3S.de/Authors/Shinobu_Fujita )