Search results for "Shmuel Wimer"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	The complexity of VLSI power-delay optimization by interconnect resizing.	J. Comb. Optim.	2012	DBLP DOI BibTeX RDF
1	Ben Emanuel, Shmuel Wimer, Gershon Wolansky	Using well-solvable quadratic assignment problems for VLSI interconnect applications.	Discrete Applied Mathematics	2012	DBLP DOI BibTeX RDF
1	Eranda Çela, Nina S. Schmuck, Shmuel Wimer, Gerhard J. Woeginger	The Wiener maximum quadratic assignment problem.	Discrete Optimization	2011	DBLP DOI BibTeX RDF
1	Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer	A Cost Effective Centralized Adaptive Routing for Networks-on-Chip.	DSD	2011	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect Bundle Sizing Under Discrete Design Rules.	IEEE Trans. on CAD of Integrated Circuits and Systems	2010	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Interconnect power and delay optimization by dynamic programming in gridded design rules.	ISPD	2010	DBLP DOI BibTeX RDF	gridded design rules, interconnect sizing and spacing, power-delay optimization, dynamic programming, interconnect optimization
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Power-delay optimization in VLSI microprocessors by wire spacing.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Wire spacing, power optimization, interconnect optimization, delay-optimization
1	Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer	Timing-aware power-optimal ordering of signals.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	Wire ordering, wire spacing, power optimization, interconnect optimization
1	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	On optimal ordering of signals in parallel wire bundles.	Integration	2008	DBLP DOI BibTeX RDF
1	Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny	Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Jack A. Feldman, Israel A. Wagner, Shmuel Wimer	An efficient algorithm for some multirow layout problems.	IEEE Trans. on CAD of Integrated Circuits and Systems	1993	DBLP DOI BibTeX RDF
1	Shmuel Wimer, Israel Koren, Israel Cederbaum	On Paths with the Shortest Average Arc Length in Weighted Graphs.	Discrete Applied Mathematics	1993	DBLP DOI BibTeX RDF
1	Israel Cederbaum, Israel Koren, Shmuel Wimer	Balanced Block Spacing for VLSI Layout.	Discrete Applied Mathematics	1992	DBLP BibTeX RDF
1	Reuven Bar-Yehuda, Jack A. Feldman, Ron Y. Pinter, Shmuel Wimer	Depth-first-search and dynamic programming algorithms for efficient CMOS cell generation.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Shmuel Wimer, Israel Koren, Israel Cederbaum	Optimal aspect ratios of building blocks in VLSI.	IEEE Trans. on CAD of Integrated Circuits and Systems	1989	DBLP DOI BibTeX RDF
1	Shmuel Wimer, Israel Koren	Analysis of strategies for constructive general block placement.	IEEE Trans. on CAD of Integrated Circuits and Systems	1988	DBLP DOI BibTeX RDF
1	Shmuel Wimer, Israel Koren, Israel Cederbaum	Optimal Aspect Ratios of Building Blocks in VLSI.	DAC	1988	DBLP BibTeX RDF
1	Shmuel Wimer, Ron Y. Pinter, Jack A. Feldman	Optimal Chaining of CMOS Transistors in a Functional Cell.	IEEE Trans. on CAD of Integrated Circuits and Systems	1987	DBLP DOI BibTeX RDF
1	Shmuel Wimer, N. Sharfman	HOPLA-PLA optimization and synthesis.	DAC	1983	DBLP BibTeX RDF

Publications of "Shmuel Wimer" ( http://dblp.L3S.de/Authors/Shmuel_Wimer )