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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 12 publication records. Showing 12 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.  |
IEICE Transactions  |
2011 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama |
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? |
Multiple-Valued Logic and Soft Computing |
2011 |
DBLP BibTeX RDF |
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| 1 | Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. |
ASP-DAC |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. |
IEICE Transactions |
2010 |
DBLP BibTeX RDF |
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| 1 | Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama |
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. |
ERSA |
2010 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama |
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. |
ERSA |
2009 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama |
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. |
ERSA |
2009 |
DBLP BibTeX RDF |
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| 1 | Shota Ishihara, Masanori Hariyama, Michitaka Kameyama |
A low-power FPGA based on autonomous fine-grain power-gating. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Masanori Hariyama, Shota Ishihara, Michitaka Kameyama |
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. |
IEICE Transactions |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama |
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. |
ERSA |
2008 |
DBLP BibTeX RDF |
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Displaying result #1 - #12 of 12 (100 per page; Change: )
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