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Publications of "Siva Kumar Sastry Hari" ( http://dblp.L3S.de/Authors/Siva_Kumar_Sastry_Hari )

  Author page on DBLP  Author page in RDF  Community of Siva Kumar Sastry Hari in ASPL-2

Publication years (Num. hits)
2007 (1) 2008 (1) 2009 (2) 2011 (1) 2012 (2)
Publication types (Num. hits)
article(1) inproceedings(6)
Venues (Conferences, Journals, ...)
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Found 7 publication records. Showing 7 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
1Siva Kumar Sastry Hari, Sarita V. Adve, Helia Naeimi, Pradeep Ramachandran Relyzer: exploiting application-level fault equivalence to analyze application resiliency to transient faults. Search on Bibsonomy ASPLOS The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
1Andrea Pellegrini, Robert Smolinski, Lei Chen, Xin Fu, Siva Kumar Sastry Hari, Junhao Jiang, Sarita V. Adve, Todd M. Austin, Valeria Bertacco CrashTest'ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. Search on Bibsonomy DATE The full citation details ... 2012 DBLP  BibTeX  RDF
1Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel J. Sorin, Albert Meixner, A. Biswas, Xavier Vera Architectures for online error detection and recovery in multicore processors. Search on Bibsonomy DATE The full citation details ... 2011 DBLP  BibTeX  RDF
1Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve mSWAT: low-cost hardware fault detection and diagnosis for multicore systems. Search on Bibsonomy MICRO The full citation details ... 2009 DBLP  DOI  BibTeX  RDF architecture, error detection, fault injection, multicore processors
1Man-Lap Li, Pradeep Ramachandran, Ulya R. Karpuzcu, Siva Kumar Sastry Hari, Sarita V. Adve Accurate microarchitecture-level fault modeling for studying hardware faults. Search on Bibsonomy HPCA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
1Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil Automatic Constraint Based Test Generation for Behavioral HDL Models. Search on Bibsonomy IEEE Trans. VLSI Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
1K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula Power Virus Generation Using Behavioral Models of Circuits. Search on Bibsonomy VTS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Dynamic power dissipation, Power virus, Integer Constraint Solvers, Hardware Description Languages (HDL), Behavioral Models
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