Search results for "Somnath Paul"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Lei Wang, Somnath Paul, Swarup Bhunia	Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Anandaroop Ghosh, Somnath Paul, Swarup Bhunia	Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Somnath Paul, Fang Cai, Xinmiao Zhang, Swarup Bhunia	Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache.	IEEE Trans. Computers	2011	DBLP DOI BibTeX RDF
1	Somnath Paul, Swarup Bhunia	Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Somnath Paul, Swarup Bhunia	Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only).	FPGA	2011	DBLP DOI BibTeX RDF
1	Somnath Paul, Hamid Mahmoodi, Swarup Bhunia	Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection.	ACM Trans. Design Autom. Electr. Syst.	2010	DBLP DOI BibTeX RDF
1	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
1	Seetharam Narasimhan, Rajat Subhra Chakraborty, Dongdong Du, Somnath Paul, Francis G. Wolff, Christos A. Papachristou, Kaushik Roy, Swarup Bhunia	Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach.	HOST	2010	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Somnath Paul, Yu Zhou, Swarup Bhunia	Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping.	IET Computers & Digital Techniques	2009	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Francis G. Wolff, Somnath Paul, Christos A. Papachristou, Swarup Bhunia	MERO: A Statistical Approach for Hardware Trojan Detection.	CHES	2009	DBLP DOI BibTeX RDF
1	Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia	A variation-aware preferential design approach for memory based reconfigurable computing.	ICCAD	2009	DBLP BibTeX RDF
1	Somnath Paul, Subho Chatterjee, Saibal Mukhopadhyay, Swarup Bhunia	A circuit-software co-design approach for improving EDP in reconfigurable frameworks.	ICCAD	2009	DBLP BibTeX RDF
1	Yu Zhou, Somnath Paul, Swarup Bhunia	Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect.	ISQED	2008	DBLP DOI BibTeX RDF
1	Somnath Paul, Swarup Bhunia	Reconfigurable computing using content addressable memory for improved performance and resource usage.	DAC	2008	DBLP DOI BibTeX RDF	field programmable gate array (FPGA), content addressable memory, resource utilization
1	Seetharam Narasimhan, Somnath Paul, Swarup Bhunia	Collective computing based on swarm intelligence.	DAC	2008	DBLP DOI BibTeX RDF	collective intelligence, adaptive computing, multi-processor
1	Somnath Paul, Swarup Bhunia	MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF	Diode-resistor logic, logic-level degradation, nano-crossbar circuit, robust circuit design
1	Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia	On-Demand Transparency for Improving Hardware Trojan Detectability.	HOST	2008	DBLP DOI BibTeX RDF
1	Yu Zhou, Somnath Paul, Swarup Bhunia	Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement.	DATE	2008	DBLP DOI BibTeX RDF
1	Somnath Paul, Saibal Mukhopadhyay, Swarup Bhunia	Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches.	ICCAD	2008	DBLP DOI BibTeX RDF	STTRAM, emerging memory technologies, nonvolatile FPGA
1	Sivasubramaniam Krishnamurthy, Somnath Paul, Swarup Bhunia	Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration.	ISQED	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips.	VTS	2007	DBLP DOI BibTeX RDF	scan-based DFT, security, detection probability, low overhead, cryptographic hardware
1	Somnath Paul, Rajat Subhra Chakraborty, Swarup Bhunia	Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid Mahmoodi, Swarup Bhunia	Low-overhead design technique for calibration of maximum frequency at multiple operating points.	ICCAD	2007	DBLP DOI BibTeX RDF	frequency calibration, voltage sensitivity, dynamic voltage and frequency scaling, ring oscillator
1	Somnath Paul, Swarup Bhunia	Memory based computation using embedded cache for processor yield and reliability improvement.	ICCD	2007	DBLP DOI BibTeX RDF
1	Pradeep K. Mishra, Somnath Paul, S. Venkataraman, Rajat Gupta	Hardware/Software Co-design of a High-end Mixed Signal Microcontroller.	VLSI Design	1998	DBLP DOI BibTeX RDF	Mixed sigal microcontroller, Signal Processing, Hardware/Software Co-design

Publications of "Somnath Paul" ( http://dblp.L3S.de/Authors/Somnath_Paul )