Search results for "Soo-Ik Chae"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Daewoong Kim, Kilhyung Cha, Doo-Seung Hong, Soonwoo Choi, Soo-Ik Chae	A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models.	EURASIP J. Emb. Sys.	2011	DBLP DOI BibTeX RDF
1	Soonwoo Choi, Jason J. K. Park, Moonmo Koo, Daewoong Kim, Soo-Ik Chae	A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor.	SoCC	2010	DBLP DOI BibTeX RDF
1	Daewoong Kim, Kilhyung Cha, Soo-Ik Chae	Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Jinhyun Cho, Doowon Lee, Sang-yong Yoon, Sanggyu Park, Soo-Ik Chae	VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications.	IEICE Transactions	2009	DBLP BibTeX RDF
1	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A mixed-level virtual prototyping environment for SystemC-based design methodology.	Microelectronics Journal	2009	DBLP DOI BibTeX RDF
1	Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Katalin Popovici, Xavier Guerin, Ahmed Amine Jerraya, Kai Huang, Lei Li, Xiaolang Yan	Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation.	Integration	2009	DBLP DOI BibTeX RDF
1	Daewoong Kim, Kilhyung Cha, Soonwoo Choi, Soo-Ik Chae	Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks.	SiPS	2009	DBLP DOI BibTeX RDF
1	Sang-yong Yoon, Soo-Ik Chae	Cache Optimization for H.264/AVC Motion Compensation.	IEICE Transactions	2008	DBLP DOI BibTeX RDF
1	Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae	RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow.	FDL	2008	DBLP DOI BibTeX RDF
1	Sang-Il Han, Soo-Ik Chae, Lisane B. de Brisolara, Luigi Carro, Ricardo Reis, Xavier Guerin, Ahmed Amine Jerraya	Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.	Design Autom. for Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya	Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.	SCOPES	2007	DBLP DOI BibTeX RDF
1	Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya	Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264.	DAC	2007	DBLP DOI BibTeX RDF
1	Seokkee Kim, Soo-Ik Chae	A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications.	IEICE Transactions	2006	DBLP DOI BibTeX RDF
1	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
1	Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya	Buffer memory optimization for video codec application modeled in Simulink.	DAC	2006	DBLP DOI BibTeX RDF	memory size reduction, video codec application, Simulink
1	Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya	Functional modeling techniques for efficient SW code generation of video codec applications.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae	Reusable component IP design using refinement-based design environment.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Ren Huang, Soo-Ik Chae	Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring.	CIT	2006	DBLP DOI BibTeX RDF
1	Sanggyu Park, Soo-Ik Chae	A Two-Week Program for a Platform-Based SoC Design.	MSE	2005	DBLP DOI BibTeX RDF
1	Sanggyu Park, Soo-Ik Chae	A C/C++-Based Functional Verification Framework Using the SystemC Verification Library.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
1	Seokkee Kim, Soo-Ik Chae	Complexity reduction in an nRERL microprocessor.	ISLPED	2005	DBLP DOI BibTeX RDF	buffer skipping, clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), reversibility breaking, microprocessor, complexity reduction
1	Seokkee Kim, Soo-Ik Chae	Implementation of a simple 8-bit microprocessor with reversible energy recovery logic.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	clocked power generator (CPG), nMOS reversible energy recovery logic (nRERL), phase scheduling, reversibility breaking, microprocessor
1	Minho Kim, Ingu Hwang, Soo-Ik Chae	A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Eunseok Song, Young-Kil Park, Soon Kwon, Soo-Ik Chae	A Cycle-Accurate Energy Estimator for CMOS Digital Circuits.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya	An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory.	DAC	2004	DBLP DOI BibTeX RDF	data transfer architecture, memory server, message passing, network on chip, network interface, multiprocessor SoC
1	Yongjin Ahn, Daehong Kim, Sunghyun Lee, Sanggyu Park, Sungjoo Yoo, Kiyoung Choi, Soo-Ik Chae	An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design.	Design Autom. for Emb. Sys.	2003	DBLP DOI BibTeX RDF
1	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of application-specific systems.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae	An 8-b nRERL microprocessor for ultra-low-energy applications.	ASP-DAC	2001	DBLP DOI BibTeX RDF
1	Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae	Emulator Environment Based on an FPGA Prototyping Board. (PDF / PS)	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	virtual ware, FPGA, emulator
1	Koichi Nose, Soo-Ik Chae, Takayasu Sakurai	Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).	ISLPED	2000	DBLP DOI BibTeX RDF	gate capacitance, low supply voltage, low-power design
1	Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae	A three-port nRERL register file for ultra-low-energy applications.	ISLPED	2000	DBLP DOI BibTeX RDF
1	Joonho Lim, Dong-G. Kim, Sang-C. Kang, Soo-Ik Chae	An 8×8 nRERL serial multiplier for ultra-low-power aplications.	ASP-DAC	2000	DBLP DOI BibTeX RDF
1	Eel-Wan Lee, Soo-Ik Chae	Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality.	IEEE Trans. Pattern Anal. Mach. Intell.	1998	DBLP DOI BibTeX RDF	NIST database, fast design, computational complexity, Nearest-neighbor classifier, triangular inequality
1	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of system level bus.	ISLPED	1998	DBLP DOI BibTeX RDF
1	Kyungmin Na, Bumki Jeon, Dong-Il Chang, Soo-Ik Chae, Souguil Ann	Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method.	EUROSPEECH	1995	DBLP BibTeX RDF
1	Kyungmin Na, Jekwan Ryu, Dong-Il Chang, Soo-Ik Chae, Souguil Ann	Recurrent neural prediction models for speech recognition.	EUROSPEECH	1995	DBLP BibTeX RDF
1	Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae	A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses.	ISCAS	1994	DBLP BibTeX RDF
1	Joonho Lim, Eel-Wan Lee, Soo-Ik Chae	Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism.	ISCAS	1994	DBLP BibTeX RDF
1	Sungjun Park, Seung-Jai Min, Soo-Ik Chae	Stereo Correspondence with Discrete-Time Cellular Neural Networks.	ISCAS	1994	DBLP BibTeX RDF
1	Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae	Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm.	ISCAS	1993	DBLP BibTeX RDF

Publications of "Soo-Ik Chae" ( http://dblp.L3S.de/Authors/Soo-Ik_Chae )