| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Michael N. Skoufis, Spyros Tragoudas |
An Online Failure Detection Method for Data Buses Using Multithreshold Receiving Logic.  |
IEEE Trans. Computers  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas |
Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission. |
Ad Hoc Networks |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ashok Kumar Palaniswamy, Spyros Tragoudas |
A scalable threshold logic synthesis method using ZBDDs. |
ACM Great Lakes Symposium on VLSI |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
Improved diagnosis using enhanced fault dominance. |
Integration |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dheepakkumaran Jayaraman, Spyros Tragoudas |
Occurrence probability analysis of a path at the architectural level. |
ISQED |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreenivas Gangadhar, Spyros Tragoudas |
An analytical method for estimating SET propagation. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis |
A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreenivas Gangadhar, Spyros Tragoudas |
A Probabilistic Approach to Diagnose SETs. |
DFT |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pragyan P. Mohanty, Spyros Tragoudas |
A Scalable Method for Identifying DNA Substrings Using Functions. |
BICoB |
2011 |
DBLP BibTeX RDF |
|
| 1 | Luke Pierce, Spyros Tragoudas |
Multi-level secure JTAG architecture. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kedar Karmarkar, Spyros Tragoudas |
Error correction encoding for multi-threshold capture mechanism. |
IOLTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas |
Scan Shift Power Reduction by Gating Internal Nodes. |
J. Low Power Electronics |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Flanigan, Spyros Tragoudas |
Identification of Delay Measurable PDFs Using Linear Dependency Relationships. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas |
Techniques to Prioritize Paths for Diagnosis. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael N. Skoufis, Kedar Karmarkar, Spyros Tragoudas, Themistoklis Haniotakis |
A Data Capturing Method for Buses on Chip. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreenivas Gangadhar, Spyros Tragoudas |
A novel probabilistic SET propagation method. |
ISQED |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Dheepakkumaran Jayaraman, Rajamani Sethuram, Spyros Tragoudas |
Gating internal nodes to reduce power during scan shift. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
gating internal nodes, scan shift power reduction, low power test |
| 1 | Ashok Kumar Palaniswamy, Manoj Kumar Goparaju, Spyros Tragoudas |
Scalable identification of threshold logic functions. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
threshold logic gates |
| 1 | Kedar Karmarkar, Spyros Tragoudas |
Scalable codeword generation for coupled buses. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Sreenivas Gangadhar, Spyros Tragoudas |
Probabilistic methods for the impact of an SET in combinational logic. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael N. Skoufis, Spyros Tragoudas |
On-line detection of random voltage perturbations in buses with multiple-threshold receivers. |
IOLTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Flanigan, Spyros Tragoudas, Arkan Abdulrahman |
Scalable Compact Test Pattern Generation for Path Delay Faults Based on Functions. |
VTS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitris Gizopoulos, Susumu Horiguchi, Spyros Tragoudas, Mohammad Tehranipoor (eds.) |
24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2009, 7-9 October 2009, Chicago, Illinois, USA |
DFT |
2009 |
DBLP BibTeX RDF |
|
| 1 | Chunrong Song, Spyros Tragoudas |
Identification of Critical Executable Paths at the Architectural Level. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyriakos Christou, Maria K. Michael, Spyros Tragoudas |
On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Zero-suppressed binary decision diagram, Irredundant sum-of-products, Critical path delay faults, Compact test generation, Delay testing, Path delay faults |
| 1 | Arkan Abdulrahman, Spyros Tragoudas |
Low-power multi-core ATPG to target concurrency. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitri Kagaris, Spyros Tragoudas |
Graph Theory and Algorithms. |
Wiley Encyclopedia of Computer Science and Engineering |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael N. Skoufis, Kedar Karmarkar, Themistoklis Haniotakis, Spyros Tragoudas |
A High-Performance Bus Architecture for Strongly Coupled Interconnects. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
high-speed bus, crosstalk |
| 1 | Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas |
A Novel Test Generation Methodology for Adaptive Diagnosis. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
Test Generation, Diagnosis, Failure Analysis |
| 1 | Edward Flanigan, Arkan Abdulrahman, Spyros Tragoudas |
Sequential Path Delay Fault Identification Using Encoded Delay Propagation Signatures. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Dheepakkumaran Jayaraman, Edward Flanigan, Spyros Tragoudas |
Implicit Identification of Non-Robustly Unsensitizable Paths using Bounded Delay Model. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Goparaju, Spyros Tragoudas |
A Novel ATPG Framework to Detect Weight Related Defects in Threshold Logic Gates. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Weght defects, ATPG, Threshold logic, Parametric faults |
| 1 | Rajsekhar Adapa, Spyros Tragoudas |
Prioritization of Paths for Diagnosis. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Goparaju, Ashok Kumar Palaniswamy, Spyros Tragoudas |
A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreenivas Gangadhar, Michael N. Skoufis, Spyros Tragoudas |
Propagation of Transients Along Sensitizable Paths. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Khadija Stewart, Spyros Tragoudas |
Managing the power resources of sensor networks with performance considerations. |
Computer Communications |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis |
Speedups in embedded systems with a high-performance coprocessor datapath. |
ACM Trans. Design Autom. Electr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
coprocessor datapath, synthesis, kernels, Performance improvements, design flow, chaining |
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
High-Quality Transition Fault ATPG for Small Delay Defects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Flanigan, Spyros Tragoudas |
Enhanced Identification of Strong Robustly Testable Paths. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov |
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Manoj Kumar Goparaju, Spyros Tragoudas |
A Fault Tolerant Design Methodology for Threshold Logic Gates and Its Optimizations. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael N. Skoufis, Haibo Wang, Themistoklis Haniotakis, Spyros Tragoudas |
Glitch Control with Dynamic Receiver Threshold Adjustment. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
Accelerating Diagnosis via Dominance Relations between Sets of Faults. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Flanigan, Rajsekhar Adapa, Hailong Cui, Michael Laisne, Spyros Tragoudas, Tsvetomir Petrov |
Function-based ATPG for Path Delay Faults using the Launch-Off-Capture Scan Architecture. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
Implicit grading of multiple path delay faults. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
Fault simulation, decision diagrams, delay fault testing |
| 1 | Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose |
InTeRail: A Test Architecture for Core-Based SOCs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
design for testability, cores, test access mechanism, System-on-chip test |
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis |
A high-performance data path for synthesizing DSP kernels. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
Functions for Quality Transition-Fault Tests and Their Applications in Test-Set Enhancement. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Flanigan, Themistoklis Haniotakis, Spyros Tragoudas |
An Improved Method for Identifying Linear Dependencies in Path Delay Faults. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas |
Minimizing FPGA Reconfiguration Data at Logic Level. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
Evaluation of Collapsing Methods for Fault Diagnosis. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Arkan Abdulrahman, Spyros Tragoudas |
Power-Aware Test Pattern Generation for Improved Concurrency at the Core Level. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Exact At-speed Delay Fault Grading in Sequential Circuits. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Khadija Stewart, Spyros Tragoudas |
Interconnect Testing for Networks on Chips. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajsekhar Adapa, Spyros Tragoudas, Maria K. Michael |
Sub-faults identification for collapsing in diagnosis. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyriakos Christou, Maria K. Michael, Spyros Tragoudas |
Implicit Critical PDF Test Generation with Maximal Test Efficiency. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas |
A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
Efficient Deterministic Test Generation for BIST Schemes with LFSR Reseeding. |
IOLTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
Low Power Test Generation for Path Delay Faults. |
J. Low Power Electronics |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis |
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. |
Journal of Circuits, Systems, and Computers |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
Efficient identification of (critical) testable path delay faults using decision diagrams. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Moiz Khan, Spyros Tragoudas |
Rewiring for watermarking digital circuit netlists. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Spyros Tragoudas, Vijay Nagarandal |
On-chip embedding mechanisms for large sets of vectors for delay test. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria K. Michael, Spyros Tragoudas |
Function-based compact test pattern generation for path delay faults. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Themistoklis Haniotakis, Spyros Tragoudas, G. Pani |
Reduced Test Application Time Based on Reachability Analysis. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Welling, Spyros Tragoudas, Haibo Wang |
A Minimum Cut Based Re-Synthesis Approach. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Khadija Stewart, Themistoklis Haniotakis, Spyros Tragoudas |
Design and Evaluation of a Security Scheme for Sensor Networks. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria K. Michael, Stelios Neophytou, Spyros Tragoudas |
Functions for Quality Transition Fault Tests. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
Low power test generation for path delay faults using stability functions. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults |
| 1 | Stelios Neophytou, Maria K. Michael, Spyros Tragoudas |
Test set enhancement for quality transition faults using function-based methods. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
high quality test, ATPG, delay test, critical paths, transition fault, test compaction |
| 1 | Krishna Prasad Raghuraman, Haibo Wang, Spyros Tragoudas |
A Novel Approach to Minimizing Reconfiguration Cost for LUT-Based FPGAs. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Implicit and Exact Path Delay Fault Grading in Sequential Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas |
Quality Transition Fault Tests Suitable for Small Delay Defects. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria K. Michael, Kyriakos Christou, Spyros Tragoudas |
Towards finding path delay fault tests with high test efficiency using ZBDDs. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria K. Michael, Themistoklis Haniotakis, Spyros Tragoudas |
A unified framework for generating all propagation functions for logic errors and events. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | J. V. Deodhar, Spyros Tragoudas |
Implicit deductive fault simulation for complex delay fault models. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Costas E. Goutis |
A Novel Data-Path for Accelerating DSP Kernels. |
SAMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
An Adaptive Path Delay Fault Diagnosis Methodology. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Moiz Khan, Spyros Tragoudas |
Rewiring for Watermarking Digital Circuits. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
A Critical Path Selection Method for Delay Testing. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Haibo Wang, Suchitra Kulkarni, Spyros Tragoudas |
On-line Testing Field Programmable Analog Array Circuits. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis |
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis |
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. |
PATMOS |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Saravanan Padmanaban, Spyros Tragoudas |
Low power ATPG for path delay faults. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
low power, ATPG, path delay faults, PODEM |
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis |
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis |
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu |
Identification of Gates for Covering all Critical Paths. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Arkan Abdulrahman, Spyros Tragoudas |
Compact ATPG for Concurrent SOC Testing. |
MTV |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Spyros Tragoudas, N. Denny |
Path delay fault testing using test points. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
path delay fault simulation (coverage), testing digital circuits, design for testability, Automatic test pattern generation, delay testing, path delay fault testing |
| 1 | Saravanan Padmanaban, Maria K. Michael, Spyros Tragoudas |
Exact path delay fault coverage with fundamental ZBDD operations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
An implicit path-delay fault diagnosis methodology. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitri Kagaris, Spyros Tragoudas |
LFSR Characteristic Polynomials for Pseudo-Exhaustive TPG with Low Number of Seeds. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
built-in self-test (BIST), Linear Feedback Shift Registers (LFSR), test pattern generation (TPG) |
| 1 | Maria K. Michael, Spyros Tragoudas |
Generation of Hazard Identification Functions. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Saravanan Padmanaban, Spyros Tragoudas |
Non-Enumerative Path Delay Fault Diagnosis . |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Dimitri Kagaris, Spyros Tragoudas |
InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Spyros Tragoudas, Yaakov L. Varol |
Disjoint Paths with Length Constraints. |
I. J. Comput. Appl. |
2002 |
DBLP BibTeX RDF |
|
| 1 | Turgay Korkmaz, Marwan Krunz, Spyros Tragoudas |
An efficient algorithm for finding a path subject to two additive constraints. |
Computer Communications |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Maria K. Michael, Spyros Tragoudas |
ATPG tools for delay faults at the functional level. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
functional-level testing, path delay fault simulation (coverage), testing digital circuits, Automatic test pattern generation, Binary Decision Diagrams, delay testing, Boolean Satisfiability, path delay fault testing |
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