Search results for "Sreehari Veeramachaneni"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Prefix Based Reconfigurable Adder.	ISVLSI	2011	DBLP DOI BibTeX RDF
1	Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Unified Architecture for BCD and Binary Adder/Subtractor.	DSD	2011	DBLP DOI BibTeX RDF
1	Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas	An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.	J. Low Power Electronics	2010	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.	ISVLSI	2010	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas	A low power, variable resolution two-step flash ADC.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	two-step flash ADC, variable resolution, low power
1	Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.	VLSI Design	2010	DBLP DOI BibTeX RDF	delay reduction, Schmitt Trigger, Buffer Insertion, Power reduction
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas	A High Performance Unified BCD and Binary Adder/Subtractor.	ISVLSI	2009	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas	Design of a Low Power, Variable-Resolution Flash ADC.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas	A novel low power, variable resolution pipelined ADC.	SoCC	2009	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.	ISVLSI	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas	Novel architectures for efficient (m, n) parallel counters.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	low power, multiplexer, high speed, parallel counters
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas	Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.	ISCAS	2007	DBLP DOI BibTeX RDF

Publications of "Sreehari Veeramachaneni" ( http://dblp.L3S.de/Authors/Sreehari_Veeramachaneni )