| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Hassan Salmani, Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty, Patrick Girard, Xiaoqing Wen |
Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of Transition Delay Fault Patterns.  |
J. Low Power Electronics  |
2012 |
DBLP BibTeX RDF |
|
| 1 | Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty |
Ensuring Power-Safe Application of Test Patterns Using an Effective Gating Approach Considering Current Limits. |
J. Low Power Electronics |
2012 |
DBLP BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas |
Optimal manufacturing flow to determine minumum operating voltage. |
ITC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
A Process Monitor Based Speed Binning and Die Matching Algorithm. |
Asian Test Symposium |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhao, Mohammad Tehranipoor, Sreejit Chakravarty |
Power-safe test application using an effective gating approach considering current limits. |
VTS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty |
Testing of latch based embedded arrays using scan tests. |
ITC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Wei Zhao, Junxia Ma, Mohammad Tehranipoor, Sreejit Chakravarty |
Power-Safe Application of Transition Delay Fault Patterns Considering Current Limit during Wafer Test. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh |
Modified Scan Flip-Flop for Low Power Testing. |
Asian Test Symposium |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
Special session 11C: Hot topic design consideration and silicon evaluation of on-chip monitors. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sean H. Wu, Sreejit Chakravarty, Li-C. Wang |
Impact of multiple input switching on delay test under process variation. |
VTS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty |
Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detectability of internal bridging faults in scan chains. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicholas Callegari, Pouria Bastani, Li-C. Wang, Sreejit Chakravarty, Alexander Tetelbaum |
Path selection for monitoring unexpected systematic timing effects. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Improving the Detectability of Resistive Open Faults in Scan Cells. |
DFT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty |
A Methodology for Handling Complex Functional Constraints for Large Industrial Designs. |
J. Electronic Testing |
2008 |
DBLP DOI BibTeX RDF |
Untestability analysis, Pseudo-functional tests, Functional constraints |
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Internal Stuck-open Faults in Scan Chains. |
ITC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
On the Detectability of Scan Chain Internal Faults An Industrial Case Study. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Faults in scan cells, stuck-at and stuck-on faults |
| 1 | I-De Huang, Yi-Shing Chang, Sandeep K. Gupta, Sreejit Chakravarty |
An Industrial Case Study of Sticky Path-Delay Faults. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
sticky paths, timing false paths, path reprioritization, delay testing, test quality |
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. |
DFT |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz |
An Enhanced Logic BIST Architecture for Online Testing. |
IOLTS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Exact Delay Fault Coverage in Sequential Logic Under Any Delay Fault Model. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Exact At-speed Delay Fault Grading in Sequential Circuits. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Manan Syal, Kameshwar Chandrasekar, Vishnu C. Vimjam, Michael S. Hsiao, Yi-Shing Chang, Sreejit Chakravarty |
A Study of Implication Based Pseudo Functional Testing. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty |
Path Delay Fault Simulation on Large Industrial Designs. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric N. Tran, Vishwashanth Kasulasrinivas, Sreejit Chakravarty |
Silicon Evaluation of Logic Proximity Bridge Patterns. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty |
An Approach to Minimizing Functional Constraints. |
DFT |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Efficient techniques for transition testing. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
test chain, test data volume reduction, transition faults, Test application time reduction, yield loss |
| 1 | Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty |
Logic proximity bridges. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Manan Syal, Michael S. Hsiao, Suriyaprakash Natarajan, Sreejit Chakravarty |
Untestable Multi-Cycle Path Delay Faults in Industrial Designs. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
Improving Logic Test Quality of Microprocessors. |
Asian Test Symposium |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Yi-Shing Chang, Hiep Hoang, Sridhar Jayaraman, Silvio Picano, Cheryl Prunty, Eric W. Savage, Rehan Sheikh, Eric N. Tran, Khen Wee |
Experimental Evaluation of Bridge Patterns for a High Performance Microprocessor. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Shing Chang, Sreejit Chakravarty, Hiep Hoang, Nick Thorpe, Khen Wee |
Transition Tests for High Performance Microprocessors. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas, Sreejit Chakravarty, Rathish Jayabharathi |
Implicit and Exact Path Delay Fault Grading in Sequential Circuits. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty |
Extraction of two-node bridges from large industrial circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Eric W. Savage, Eric N. Tran |
Defect Coverage Analysis of Partitioned Testing. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Manan Syal, Michael S. Hsiao, Sreejit Chakravarty |
Identifying Untestable Transition Faults in Latch Based Designs with Multiple Clocks. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty |
Algorithm to extract two-node bridges. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
stuck-at vectors, delay testing, transition fault |
| 1 | Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, Sreejit Chakravarty |
Efficient Implication - Based Untestable Bridge Fault Identifier. |
VTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
Supplemental Test Methods (Tutorial Abstract). (PDF / PS) |
ISQED |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Ankur Jain, Nandakumar Radhakrishnan, Eric W. Savage, Sujit T. Zachariah |
Experimental Evaluation of Scan Tests for Bridges. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Liu, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran |
Techniques to Reduce Data Volume and Application Time for Transition Test. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Kambiz Komeyli, Eric W. Savage, Michael J. Carruthers, Bret T. Stastny, Sujit T. Zachariah |
Layout Analysis to Extract Open Nets Caused by Systematic Failure Mechanisms. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Ankur Jain |
Fault Models for Speed Failures Caused by Bridges and Opens. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty |
Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
stuck-at fault diagnosis, Fault simulation |
| 1 | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
Automatic generation and compaction of March tests for memory arrays. |
IEEE Trans. VLSI Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty |
A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Sujit T. Zachariah |
STBM: a fast algorithm to simulate IDDQ tests forleakage faults. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty |
A scalable and efficient methodology to extract two node bridges from large industrial circuits. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota |
An analysis of the delay defect detection capability of the ECR test method. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty, Carl D. Roth |
A novel algorithm to extract two-node bridges. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Vinodh Gopal |
Techniques to Encode and Compress Fault Dictionaries. |
VTS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit T. Zachariah, Sreejit Chakravarty |
A Comparative Study of Pseudo Stuck-At and Leakage Fault Model. |
VLSI Design |
1999 |
DBLP BibTeX RDF |
|
| 1 | Sreenivas Mandava, Sreejit Chakravarty, Sandip Kundu |
On Detecting Bridges Causing Timing Failures. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
Resistive Bridges, Timing Failures, Transition Fault Model, Delay Test, At-Speed Testing, Low Voltage Testing |
| 1 | Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy |
Techniques for minimizing power dissipation in scan and combinational circuits during test application. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiming Gong, Sreejit Chakravarty |
Locating bridging faults using dynamically computed stuck-at fault dictionaries. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty |
A new framework for generating optimal March tests for memory arrays. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Dabholkar, Sreejit Chakravarty |
Computing Stress Tests for Gate Oxide Shorts. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
burn-in, stress tests, gate oxide shorts |
| 1 | Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel |
Algorithms to compute bridging fault coverage of IDDQ test sets. |
ACM Trans. Design Autom. Electr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Dabholkar, Sreejit Chakravarty |
Computing stress tests for interconnect defects. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
interconnect defects, reliability screens, infant mortality, gate-oxide defects, integrated circuit testing, stress tests |
| 1 | Sreejit Chakravarty |
On the capability of delay tests to detect bridges and opens. |
Asian Test Symposium |
1997 |
DBLP DOI BibTeX RDF |
defective IC, faulty dynamic logic behavior, transition tests, simulation, integrated circuit testing, delay tests, bridges, opens, at-speed testing, path delay tests |
| 1 | Yiming Gong, Sreejit Chakravarty |
Using fault sampling to compute I/sub DDQ/ diagnostic test set. |
VTS |
1997 |
DBLP DOI BibTeX RDF |
fault sampling, IDDQ diagnostic test set generation, combinational circuits, combinational circuit, bridging faults |
| 1 | Sreejit Chakravarty |
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Paul J. Thadikaran |
Simulation and Generation of IDDQ Tests for Bridging Faults in Combinational Circuits. |
IEEE Trans. Computers |
1996 |
DBLP DOI BibTeX RDF |
test generation, fault simulation, Bridging faults, IDDQ testing |
| 1 | Sreejit Chakravarty, Yiming Gong, Srikanth Venkataraman |
Diagnostic simulation of stuck-at faults in combinational circuits. |
J. Electronic Testing |
1996 |
DBLP DOI BibTeX RDF |
diagnostic power, diagnostic simulation, diagnosis, equivalence classes, diagnostic resolution |
| 1 | Sreejit Chakravarty, Paul J. Thadikaran |
Algorithms to select IDDQ measurement points to detect bridging faults. |
J. Electronic Testing |
1996 |
DBLP DOI BibTeX RDF |
bridging faults, test selection, I DDQ test |
| 1 | Sreejit Chakravarty |
A sampling technique for diagnostic fault simulation. |
VTS |
1996 |
DBLP DOI BibTeX RDF |
diagnostic fault simulation, diagnostic test sets, EC/IC Sampling, indistinguishable classes, approximation algorithm, fault diagnosis, integrated circuit testing, circuit analysis computing, set theory, equivalence classes, equivalence classes, sampling technique |
| 1 | Paul J. Thadikaran, Sreejit Chakravarty |
Fast Algorithms for Computer IDDQ Tests for Combination Circuits. |
VLSI Design |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Ramalingam Sridhar, Shambhu J. Upadhyaya, Yervant Zorian, Gil Philips, Bozena Kaminska, Bernard Courtois |
Conference Reports. |
IEEE Design & Test of Computers |
1995 |
DBLP BibTeX RDF |
|
| 1 | Srikanth Venkataraman, Ismed Hartanto, W. Kent Fuchs, Elizabeth M. Rudnick, Sreejit Chakravarty, Janak H. Patel |
Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits Using Compact Lists. |
DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel |
Cyclic stress tests for full scan circuits. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
cyclic stress tests, fully testable unpackaged dies, burn-in process, cyclic input sequences, stress related problems, ISCAS89 benchmark circuits, monitored burn-in problems, IC reliability, VLSI, VLSI, logic testing, integrated circuit testing, CMOS, CMOS logic circuits, boundary scan testing, MCMs, integrated circuit reliability, full scan circuits |
| 1 | Sreejit Chakravarty, Yiming Gong |
Voting model based diagnosis of bridging faults in combinational circuits. |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
MOS logic circuits, voting model based diagnosis, fault list, stuck-at fault dictionary, fault dropping rules, time efficiency, fault diagnosis, logic testing, combinational circuits, combinational circuits, bridging faults, diagnosis algorithm, space efficiency, majority logic, compact data structure |
| 1 | Paul J. Thadikaran, Sreejit Chakravarty, Janak H. Patel |
Fault Simulation ofIDDQ Tests for Bridging Faults in Sequential Circuits. |
FTCS |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Yiming Gong, Sreejit Chakravarty |
On adaptive diagnostic test generation. |
ICCAD |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Paul J. Thadikaran |
A Study of IDDQ Subset Selection Algorithms for Bridging Faults. |
ITC |
1994 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Sivaprakasam Suresh |
IDDQ Measurement Based Diagnosis of Bridging Faults in Full Scan Circuits. |
VLSI Design |
1994 |
DBLP BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
A Characterization of Binary Decision Diagrams. |
IEEE Trans. Computers |
1993 |
DBLP DOI BibTeX RDF |
repeated variables, simulation, complexity, testing, logic testing, Boolean functions, Boolean functions, synthesis, logic design, binary decision diagrams, logic circuits, characterization, computational problems |
| 1 | Sreejit Chakravarty, Yiming Gong |
An Algorithm for Diagnosing Two-Line Bridging Faults in Combinational Circuits. |
DAC |
1993 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Ajay Shekhawat |
Parallel and serial heuristics for the minimum set cover problem. |
The Journal of Supercomputing |
1992 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Minsheng Liu |
Algorithms for IDDQ measurement based diagnosis of bridging faults. |
J. Electronic Testing |
1992 |
DBLP DOI BibTeX RDF |
Bridging faults, diagnosis algorithm, I DDQ testing |
| 1 | Sreejit Chakravarty, Minsheng Liu |
Algorithms for Current Monitor Based Diagnosis of Bridging and Leakage Faults. |
DAC |
1992 |
DBLP BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Xin He, S. S. Ravi |
Minimum area layout of series-parallel transistor networks is NP-hard. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1991 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
A characterization of robust test-pairs for stuck-open faults. |
J. Electronic Testing |
1991 |
DBLP DOI BibTeX RDF |
fault simulation, robust tests, stuck-open faults, test generation algorithms |
| 1 | Sreejit Chakravarty, Harry B. Hunt III |
On Computing Signal Probability and Detection Probability of Stuck-at Faults. |
IEEE Trans. Computers |
1990 |
DBLP DOI BibTeX RDF |
pseudo gates, logic testing, built-in self test, combinational circuits, random testing, stuck-at faults, combinatorial circuits, testability analysis, detection probability, signal probability, pseudorandom testing, enumeration algorithm |
| 1 | Sreejit Chakravarty, S. S. Ravi |
Computing optimal test sequences from complete test sets for stuck-open faults in CMOS circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
On Synthesizing and Identifying Stuck-Open Testable CMOS Combinational Circuits (extended abstract). |
DAC |
1990 |
DBLP DOI BibTeX RDF |
|
| 1 | Ajay Shekhawat, Sreejit Chakravarty |
Heuristics for the MSC Problem for Serial and Shared-Memory Computers. |
ICPP |
1990 |
DBLP BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Harry B. Hunt III |
A Note on Detecting Sneak Paths in Transistor Networks. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Harry B. Hunt III, S. S. Ravi, Daniel J. Rosenkrantz |
The Complexity of Generating Minimum Test Sets for PLA's and Monotone Combinational Circuits. |
IEEE Trans. Computers |
1989 |
DBLP DOI BibTeX RDF |
minimum test sets, monotone combinational circuits, minimum complete test set, monotone PLAs, computational complexity, complexity, logic testing, NP-complete, logic arrays, combinatorial circuits, literals |
| 1 | Sreejit Chakravarty |
On the complexity of computing tests for CMOS gates. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty |
A Testable Realization of CMOS Combinational Circuits. |
ITC |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Shambhu J. Upadhyaya |
A Unified Approach to Designing Fault-Tolerant Processor Ensembles. |
ICPP |
1988 |
DBLP BibTeX RDF |
|
| 1 | Sreejit Chakravarty, Harry B. Hunt III |
On the Computation of Detection Probability for Multiple Faults. |
ITC |
1986 |
DBLP BibTeX RDF |
|
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