| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Liang Tang, Jorgen Peddersen, Sri Parameswaran |
A Rapid Methodology for Multi-mode Communication Circuit Generation.  |
VLSI Design  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Tuo Li, Roshan G. Ragel, Sri Parameswaran |
Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Roshan G. Ragel, Sri Parameswaran |
A hybrid hardware-software technique to improve reliability in embedded processors. |
ACM Trans. Embedded Comput. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic |
Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. |
IET Computers & Digital Techniques |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Krutartha Patel, Sri Parameswaran, Roshan G. Ragel |
Architectural Frameworks for Security and Reliability of MPSoCs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Yee Jern Chong, Sri Parameswaran |
Configurable Multimode Embedded Floating-Point Units for FPGAs. |
IEEE Trans. VLSI Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Haris Javaid, Muhammad Shafique, Sri Parameswaran, Jörg Henkel |
Low-power adaptive pipelined MPSoCs for multimedia: an H.264 video encoder case study. |
DAC |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Su Myat Min, Jorgen Peddersen, Sri Parameswaran |
Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Hong Chinh Doan, Haris Javaid, Sri Parameswaran |
Multi-ASIP based parallel and scalable implementation of motion estimation kernel for high definition videos. |
ESTImedia |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Sri Parameswaran |
CIPARSim: Cache intersection property assisted rapid single-pass FIFO cache simulation technique. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Haris Javaid, Muhammad Shafique, Jörg Henkel, Sri Parameswaran |
System-level application-aware dynamic power management in adaptive pipelined MPSoCs for multimedia. |
ICCAD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jörg Henkel, Sri Parameswaran |
CASES 2009 guest editor's introduction. |
Design Autom. for Emb. Sys. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM. |
Design Autom. for Emb. Sys. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Guo, Sri Parameswaran |
Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems. |
Journal of Systems Architecture - Embedded Systems Design |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
Rapid Design Space Exploration of Application Specific Heterogeneous Pipelined Multiprocessor Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
miss rate, simulation, round robin, cache simulation, L1 cache |
| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
Improved Architectures for Range Encoding in Packet Classification System. |
NCA |
2010 |
DBLP DOI BibTeX RDF |
Range Encoding, LOP, Packet Classification |
| 1 | Roshan G. Ragel, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran |
RACE: A Rapid, ArChitectural Simulation and Synthesis Framework for Embedded Processors. |
DIPES/BICC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Mohammad Shihabul Haque, Jorgen Peddersen, Andhi Janapsatya, Sri Parameswaran |
DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Haris Javaid, Andhi Janapsatya, Mohammad Shihabul Haque, Sri Parameswaran |
Rapid runtime estimation methods for pipelined MPSoCs. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Jorgen Peddersen, Sri Parameswaran |
Dueling CLOCK: Adaptive cache replacement policy based on the CLOCK algorithm. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran |
Fidelity metrics for estimation models. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haris Javaid, Xin He, Aleksandar Ignjatovic, Sri Parameswaran |
Optimal synthesis of latency and throughput constrained pipelined MPSoCs targeting streaming applications. |
CODES+ISSS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
Provably correct on-chip communication: A formal approach to automatic protocol converter synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
converter synthesis, protocol compatibility, System-on-chip, automatic design |
| 1 | Yee Jern Chong, Sri Parameswaran |
Custom Floating-Point Unit Generation for Embedded Systems. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic |
HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. |
IET Computers & Digital Techniques |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Haris Javaid, Sri Parameswaran |
A design flow for application specific heterogeneous pipelined multiprocessor systems. |
DAC |
2009 |
DBLP DOI BibTeX RDF |
design space exploration, integer linear programming, MPSoCs |
| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP_RE: Range encoding for low power packet classification. |
LCN |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Jörg Henkel, Sri Parameswaran (eds.) |
Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2009, Grenoble, France, October 11-16, 2009 |
CASES |
2009 |
DBLP BibTeX RDF |
|
| 1 | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
HitME: low power Hit MEmory buffer for embedded systems. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Yee Jern Chong, Sri Parameswaran |
Flexible multi-mode embedded floating-point unit for field programmable gate arrays. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture |
| 1 | Jörg Henkel, Vijaykrishnan Narayanan, Sri Parameswaran, Roshan G. Ragel |
Security and Dependability of Embedded Systems: A Computer Architects' Perspective. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Krutartha Patel, Sri Parameswaran, Roshan G. Ragel |
CUFFS: An instruction count based architectural framework for security of MPSoCs. |
DATE |
2009 |
DBLP BibTeX RDF |
|
| 1 | Mohammad Shihabul Haque, Andhi Janapsatya, Sri Parameswaran |
SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
miss rate, simulation, LRU, cache simulation, L1 cache |
| 1 | Xin He, Jorgen Peddersen, Sri Parameswaran |
LOP: a novel SRAM-based architecture for low power and high throughput packet classification. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
low-power, packet classification, hardware design |
| 1 | Seng Lin Shee, Andrea Erdos, Sri Parameswaran |
Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG. |
International Journal of Parallel Programming |
2008 |
DBLP DOI BibTeX RDF |
design, architecture, multiprocessor, SoC, pipelines, ASIPs, heterogeneous system |
| 1 | Tilman Wolf, Sri Parameswaran |
Guest editorial for special issue on embedded system security. |
Design Autom. for Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sri Parameswaran, Tilman Wolf |
Embedded systems security - an overview. |
Design Autom. for Emb. Sys. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorgen Peddersen, Sri Parameswaran |
Energy Driven Application Self-Adaptation at Run-time. |
JCP |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorgen Peddersen, Sri Parameswaran |
Low-Impact Processor for Dynamic Runtime Power Management. |
IEEE Design & Test of Computers |
2008 |
DBLP DOI BibTeX RDF |
low-impact processor, runtime power management, power estimation, energy aware, macromodeling, counters |
| 1 | Jude Angelo Ambrose, Naeill Aldon, Aleksandar Ignjatovic, Sri Parameswaran |
Anatomy of Differential Power Analysis for AES. |
SYNASC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Krutartha Patel, Sri Parameswaran |
SHIELD: a software hardware design methodology for security and reliability of MPSoCs. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
bit flips, tensilica, architecture, multiprocessors, code injection |
| 1 | Yee Jern Chong, Sri Parameswaran |
Rapid application specific floating-point unit generation with bit-alignment. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
bit-alignment, datapath merging, floating-point |
| 1 | Jeremy Chan, Sri Parameswaran |
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Karin Avnit, Vijay D'Silva, Arcot Sowmya, S. Ramesh, Sri Parameswaran |
A Formal Approach To The Protocol Converter Problem. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic |
MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm. |
ICCAD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Krutartha Patel, Sri Parameswaran |
LOCS: a low overhead profiler-driven design flow for security of MPSoCs. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
tensilica, architecture, mpsoc, execution profile, code injection |
| 1 | Haris Javaid, Sri Parameswaran |
Synthesis of heterogeneous pipelined multiprocessor systems using ILP: jpeg case study. |
CODES+ISSS |
2008 |
DBLP DOI BibTeX RDF |
design space exploration, integer linear programming, MPSoCs |
| 1 | Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran |
RIJID: Random Code Injection to Mask Power Analysis based Side Channel Attacks. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Seng Lin Shee, Sri Parameswaran |
Design Methodology for Pipelined Heterogeneous Multiprocessor System. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorgen Peddersen, Sri Parameswaran |
CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-time. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
dynamic power optimization, CLIPPER, counter-based low impact processor, run-time power optimization, power consumption, energy consumption |
| 1 | Jorgen Peddersen, Sri Parameswaran |
Energy Driven Application SelfAdaptation. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yee Jern Chong, Sri Parameswaran |
Automatic application specific floating-point unit generation. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel |
Instruction trace compression for rapid instruction cache simulation. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran |
A smart random code injection to mask power analysis based side channel attacks. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
random instruction injection, signture identification, side channel attack, power analysis, cross correlation |
| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
Exploiting statistical information for implementation of instruction scratchpad memory in embedded system. |
IEEE Trans. VLSI Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Roshan G. Ragel, Sri Parameswaran |
IMPRES: integrated monitoring for processor reliability and security. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
basic block checksumming, bit flips detection, check sum encryption, detecting code injection attacks |
| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
A novel instruction scratchpad memory optimization method based on concomitance metric. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran |
Finding optimal L1 cache configuration for embedded systems. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ivan Siu-Chuang Lu, Neil Weste, Sri Parameswaran |
ADC Precision Requirement for Digital Ultra-Wideband Receivers with Sublinear Front-Ends: A Power and Performance Perspective. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran |
Customization of application specific heterogeneous multi-pipeline processors. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Roshan G. Ragel, Sri Parameswaran |
Hardware assisted pre-emptive control flow checking for embedded processors to improve reliability. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
embedded processor reliability, hardware/software technique, micro-instruction routines, preemptive fault detection, reliable processors, control flow checking |
| 1 | Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic |
Application specific forwarding network and instruction encoding for multi-pipe ASIPs. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
multi-pipe ASIP, VLIW, forwarding, instruction encoding |
| 1 | Seng Lin Shee, Andrea Erdos, Sri Parameswaran |
Heterogeneous multiprocessor implementations for JPEG: : a case study. |
CODES+ISSS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sri Parameswaran, Jörg Henkel |
Instruction code mapping for performance increase and energy reduction in embedded computer systems. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Guo, Sri Parameswaran |
Balancing System Level Pipelines with Stage Voltage Scaling. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia |
Micro embedded monitoring for security in application specific instruction-set processors. |
CASES |
2005 |
DBLP DOI BibTeX RDF |
micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring |
| 1 | Newton Cheung, Sri Parameswaran, Jörg Henkel |
Battery-aware instruction generation for embedded processors. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran |
Rapid Embedded Hardware/Software System Generation. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeremy Chan, Sri Parameswaran |
NoCEE: energy macro-model extraction methodology for network on chip routers. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Seng Lin Shee, Sri Parameswaran, Newton Cheung |
Novel architecture for loop acceleration: a case study. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
tightly coupled, architecture, ASIP, hardware/software partitioning, coprocessor, loop optimization, latency hiding, loop pipelining, loop acceleration |
| 1 | Jeremy Chan, Sri Parameswaran |
NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Newton Cheung, Sri Parameswaran, Jörg Henkel, Jeremy Chan |
MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Newton Cheung, Sri Parameswaran, Jörg Henkel |
A quantitative study and estimation models for extensible instructions in embedded processors. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Andhi Janapsatya, Sri Parameswaran, Aleksandar Ignjatovic |
Hardware/software managed scratchpad memory for embedded system. |
ICCAD |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran |
Dual-pipeline heterogeneous ASIP design. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
dual-pipeline, instruction set generation, ASIP, superscalar |
| 1 | Ramesh Chandra, Preeti Ranjan Panda, Jörg Henkel, Sri Parameswaran, Loganath Ramachandran |
Specification and Design of Multi-Million Gate SOCs. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Newton Cheung, Jörg Henkel, Sri Parameswaran |
Rapid Configuration and Instruction Selection for an ASIP: A Case Study. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Newton Cheung, Sri Parameswaran, Jörg Henkel |
INSIDE: INstruction Selection/Identification & Design Exploration for Extensible Processors. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Tony Han, Sri Parameswaran |
SWASAD: An ASIC Design for High Speed DNA Sequence Matching. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jörg Henkel, Xiaobo Sharon Hu, Rajesh Gupta, Sri Parameswaran (eds.) |
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, CODES 2002, Estes Park, Colorado, USA, May 6-8, 2002 |
CODES |
2002 |
DBLP BibTeX RDF |
|
| 1 | Sri Parameswaran |
Code placement in hardware/software co-synthesis to improve performance and reduce cost. |
DATE |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Sri Parameswaran, Jörg Henkel |
I-CoPES: Fast Instruction Code Placement for Embedded Systems to Improve Performance and Energy Efficiency. |
ICCAD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Sri Parameswaran, Matthew F. Parkinson, Peter L. Bartlett |
Profiling in the ASP codesign environment. |
Journal of Systems Architecture |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | V. E. Boros, Aleksandar D. Rakic, Sri Parameswaran |
High-level model of a WDMA passive optical bus for a reconfigurable multiprocessor system. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Allan Rae, Sri Parameswaran |
Voltage reduction of application-specific heterogeneous multiprocessor systems for power minimisation. |
ASP-DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Hui Guo, Sri Parameswaran |
Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Sri Parameswaran |
HW-SW Co-Synthesis: The Present and The Future (Embedded Tutorial). |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Sri Parameswaran, Hui Guo |
Power Reduction in Pipelines. |
ASP-DAC |
1998 |
DBLP BibTeX RDF |
|
| 1 | Allan Rae, Sri Parameswaran |
Application-Specific Heterogeneous Multiprocessor Synthesis Using Differential-Evolution. (PDF / PS) |
ISSS |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran |
Reclocking for high-level synthesis. |
ASP-DAC |
1995 |
DBLP DOI BibTeX RDF |
|
| 1 | Matthew F. Parkinson, Sri Parameswaran |
Profiling in the ASP codesign environment. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
Automated Synthesis and Partitioning system, Hardware/Software Codesign project, codesign environment, hardware/software codesign methodology, high-level profiling tools, virtual machines, software tools, C, computer architecture, profiling, systems analysis, circuit CAD, workstation, ASP, C code, dedicated hardware, execution profiling |
| 1 | Sayed Mohammad Kia, Sri Parameswaran |
Design automation of self checking circuits. |
EURO-DAC |
1994 |
DBLP DOI BibTeX RDF |
VHDL |
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