Search results for "Srivaths Ravi"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Design Techniques with Multiple Scan Compression CoDecs for Low Power and High Quality Scan Test.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi	Multi-CoDec Configurations for Low Power and High Quality Scan Test.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Abhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe	Methodology for early and accurate test power estimation at RTL.	ITC	2010	DBLP DOI BibTeX RDF
1	Amit Sabne, Rajesh Tiwari, Abhijeet Shrivastava, Srivaths Ravi, Rubin A. Parekhji	A generic low power scan chain wrapper for designs using scan compression.	VTS	2010	DBLP DOI BibTeX RDF
1	George Kurian, Narayana Rao, Virendra Patidar, V. Kamakoti, Srivaths Ravi	Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.	J. Low Power Electronics	2009	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Rubin A. Parekhji, Jayashree Saxena	Low Power Test for Nanometer System-on-Chips (SoCs).	J. Low Power Electronics	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Mihalis Psarakis, Miltiadis Hatzimihail, M. Maniatakos, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi	Systematic Software-Based Self-Test for Pipelined Processors.	IEEE Trans. VLSI Syst.	2008	DBLP DOI BibTeX RDF
1	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi, Rubin A. Parekhji	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.	VTS	2008	DBLP DOI BibTeX RDF	Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume
1	Anish Muttreja, Srivaths Ravi, Niraj K. Jha	Variability-Tolerant Register-Transfer Level Synthesis.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Energy-optimizing source code transformations for operating system-driven embedded software.	ACM Trans. Embedded Comput. Syst.	2007	DBLP DOI BibTeX RDF	Linux, energy consumption, source code transformations
1	Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Hybrid Simulation for Energy Estimation of Embedded Software.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Synthesis Methodology for Hybrid Custom Instruction and Coprocessor Generation for Extensible Processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Automated Energy/Performance Macromodeling of Embedded Software.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Hardware Accelerated Power Estimation	CoRR	2007	DBLP BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Generation of Heterogeneous Distributed Architectures for Memory-Intensive Applications Through High-Level Synthesis.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha	Configuration and Extension of Embedded Processors to Optimize IPSec Protocol Execution.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar	Exploring Software Partitions for Fast Security Processing on a Multiprocessor Mobile SoC.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee	Aiding Side-Channel Attacks on Cryptographic Software With Satisfiability-Based Analysis.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Hybrid Architectures for Efficient and Secure Face Authentication in Embedded Systems.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Architectural Support for Run-Time Validation of Program Data Properties.	IEEE Trans. VLSI Syst.	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi	Power-aware test: Challenges and solutions.	ITC	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Stefan Mangard	Tutorial T1: Designing Secure SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Najwa Aaraj, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Energy and execution time analysis of a software-based trusted platform module.	DATE	2007	DBLP DOI BibTeX RDF
1	Srivaths Ravi, V. R. Devanathan, Rubin A. Parekhji	Methodology for low power test pattern generation using activity threshold control logic.	ICCAD	2007	DBLP DOI BibTeX RDF
1	Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	RTL-Aware Cycle-Accurate Functional Power Estimation.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Application-specific heterogeneous multiprocessor synthesis using extensible processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Use of Computation-Unit Integrated Memories in High-Level Synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar	Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha	Satisfiability-based test generation for nonseparable RTL controller-datapath circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2006	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Study of the Energy Consumption Characteristics of Cryptographic Algorithms and Security Protocols.	IEEE Trans. Mob. Comput.	2006	DBLP DOI BibTeX RDF	energy analysis, security, embedded system, low-power, AES, RSA, security protocols, ECC, DES, handheld, SSL, Diffie-Hellman, DSA, cryptographic algorithms, 3DES
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Scalable Synthesis Methodology for Application-Specific Processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Hardware-Assisted Run-Time Monitoring for Secure Program Execution on Embedded Processors.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi	Systematic software-based self-test for pipelined processors.	DAC	2006	DBLP DOI BibTeX RDF	functional testing, software-based self-test, processor testing
1	Divya Arora, Anand Raghunathan, Srivaths Ravi, Murugan Sankaradass, Niraj K. Jha, Srimat T. Chakradhar	Software architecture exploration for high-performance security processing on a multiprocessor mobile SoC.	DAC	2006	DBLP DOI BibTeX RDF	computation offloading, software partitioning
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Ruby B. Lee, Niraj K. Jha	Impact of Configurability and Extensibility on IPSec Protocol Execution on Embedded Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF	Performance, Embedded Systems, Security Protocols, Configurability, Extensibility, Embedded Processors, IPSec, Embedded Security
1	Najwa Aaraj, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Architectures for efficient face authentication in embedded systems.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha, Ruby B. Lee	Satisfiability-based framework for enabling side-channel attacks on cryptographic software.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
1	Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Active Learning Driven Data Acquisition for Sensor Networks.	ISCC	2006	DBLP DOI BibTeX RDF
1	Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Architectural support for safe software execution on embedded processors.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	type safety, memory safety, extensible processors
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Generation of distributed logic-memory architectures through high-level synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Power emulation: a new paradigm for power estimation.	DAC	2005	DBLP DOI BibTeX RDF	simulation, FPGA, design, design methodologies, emulation, hardware acceleration, power estimation, register-transfer level, macromodels
1	Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Efficient fingerprint-based user authentication for embedded systems.	DAC	2005	DBLP DOI BibTeX RDF	embedded systems, fingerprint, user authentication, extensible processors
1	Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Hybrid simulation for embedded software energy estimation.	DAC	2005	DBLP DOI BibTeX RDF	energy macromodels, embedded software, pointers analysis, energy estimation, hybrid simulation
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	SECA: security-enhanced communication architecture.	CASES	2005	DBLP DOI BibTeX RDF	AMBA Bus, security-aware design, small embedded systems, security, communication, access control, architecture, intrusion detection, system-on-chip (SoC), attacks, bus, digital rights management (DRM)
1	Loganathan Lingappan, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha, Srimat T. Chakradhar	Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Synthesis of Application-Specific Heterogeneous Multiprocessor Architectures Using Extensible Processors.	VLSI Design	2005	DBLP DOI BibTeX RDF
1	Divya Arora, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Secure Embedded Processing through Hardware-Assisted Run-Time Monitoring.	DATE	2005	DBLP DOI BibTeX RDF
1	Joel Coburn, Srivaths Ravi, Anand Raghunathan	Hardware Accelerated Power Estimation.	DATE	2005	DBLP DOI BibTeX RDF
1	Divya Arora, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Enhancing security through hardware-assisted run-time validation of program data properties.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	data tagging, secure architectures, run-time checks
1	Srivaths Ravi, Anand Raghunathan, Paul C. Kocher, Sunil Hattangady	Security in embedded systems: Design challenges.	ACM Trans. Embedded Comput. Syst.	2004	DBLP DOI BibTeX RDF	processing requirements, security, Embedded systems, authentication, architecture, encryption, security protocols, hardware design, tamper resistance, decryption, cryptographic algorithms, security attacks, battery life
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Custom-instruction synthesis for extensible-processor platforms.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Paul C. Kocher, Ruby B. Lee, Gary McGraw, Anand Raghunathan	Security as a new dimension in embedded system design.	DAC	2004	DBLP DOI BibTeX RDF	software attacks, security, performance, design, embedded systems, architectures, cryptography, sensors, PDAs, design methodologies, security protocols, digital rights management, trusted computing, tamper resistance, viruses, battery life, security processing
1	Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha	Automated energy/performance macromodeling of embedded software.	DAC	2004	DBLP DOI BibTeX RDF	data serialization, genetic programming, regression, embedded software, symbolic, macromodeling
1	Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Energy-Optimizing Source Code Transformations for OS-driven Embedded Software.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	Tamper Resistance Mechanisms for Secure, Embedded Systems.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Lin Zhong, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Power estimation for cycle-accurate functional descriptions of hardware.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	High-level synthesis using computation-unit integrated memories.	ICCAD	2004	DBLP DOI BibTeX RDF
1	Nachiketh R. Potlapally, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Analyzing the energy consumption of security protocols.	ISLPED	2003	DBLP DOI BibTeX RDF	energy analysis, security, embedded system, low-power, AES, RSA, security protocols, ECC, DES, handheld, SSL, Diffie-Hellman, DSA, cryptographic algorithms, 3DES
1	Indradeep Ghosh, Srivaths Ravi	On automatic generation of RTL validation test benches using circuit testing techniques.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	OCCOM, RTL ATPG, RTL testing, path coverage, small validation, toggle coverage, test, testing, generation, ATPG, fault coverage, code coverage, test sets, design validation, coverage metrics, universal test sets, testbench, branch coverage
1	Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey	A scalable software-based self-test methodology for programmable processors.	DAC	2003	DBLP DOI BibTeX RDF	scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test
1	Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	Embedding Security in Wireless Embedded Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Anand Raghunathan, Srimat T. Chakradhar	Efficient RTL Power Estimation for Large Designs.	VLSI Design	2003	DBLP DOI BibTeX RDF
1	Anand Raghunathan, Srivaths Ravi, Sunil Hattangady, Jean-Jacques Quisquater	Securing Mobile Appliances: New Challenges for the System Designer.	DATE	2003	DBLP DOI BibTeX RDF
1	Yunsi Fei, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Energy Estimation for Extensible Processors.	DATE	2003	DBLP DOI BibTeX RDF
1	Davide Bertozzi, Anand Raghunathan, Luca Benini, Srivaths Ravi	Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.	DATE	2003	DBLP DOI BibTeX RDF
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	A Scalable Application-Specific Processor Synthesis Methodology.	ICCAD	2003	DBLP DOI BibTeX RDF
1	Loganathan Lingappan, Srivaths Ravi, Niraj K. Jha	Test Generation for Non-separable RTL Controller-datapath Circuits using a Satisfiability based Approach.	ICCD	2003	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Niraj K. Jha	Test synthesis of systems-on-a-chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	High-level test compaction techniques.	IEEE Trans. on CAD of Integrated Circuits and Systems	2002	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Anand Raghunathan, Nachiketh R. Potlapally, Murugan Sankaradass	System design methodologies for a wireless security processing platform.	DAC	2002	DBLP DOI BibTeX RDF	security, performance, embedded system, wireless, encryption, AES, RSA, design methodology, system architecture, platform, DES, IPSec, SSL, decryption, handset, 3DES, security processing
1	Anand Raghunathan, Nachiketh R. Potlapally, Srivaths Ravi	Securing Wireless Data: System Architecture Challenges.	ISSS	2002	DBLP DOI BibTeX RDF	WTLS, security, performance, mobile computing, embedded system, wireless communications, encryption, AES, RSA, design methodology, system architecture, platform, DES, IPSec, SSL, decryption, handset, 3DES, security processing
1	Hiroto Yasuura, Naofumi Takagi, Srivaths Ravi, Michael Torla, Catherine H. Gebotys	Special Session: Security on SoC.	ISSS	2002	DBLP DOI BibTeX RDF	sequence charts, simulation, validation methodology
1	Chao Huang, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	High-level synthesis of distributed logic-memory architectures.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Fei Sun, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha	Synthesis of custom processors based on extensible platforms.	ICCAD	2002	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	Testing of core-based systems-on-a-chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha	Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences.	IEEE Trans. on CAD of Integrated Circuits and Systems	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression-based register-transfer level testability analysis and optimization.	IEEE Trans. VLSI Syst.	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Niraj K. Jha	Fast test generation for circuits with RTL and gate-level views.	ITC	2001	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Niraj K. Jha	Synthesis of System-on-a-chip for Testability.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Vijay Raghunathan, Srivaths Ravi, Anand Raghunathan, Ganesh Lakshminarayana	Transient Power Management Through High Level Synthesis.	ICCAD	2001	DBLP BibTeX RDF
1	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana	Integrating variable-latency components into high-level synthesis.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2000	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	: Reducing test application time in high-level test generation.	ITC	2000	DBLP DOI BibTeX RDF
1	Vijay Raghunathan, Srivaths Ravi, Ganesh Lakshminarayana	High-Level Synthesis with Variable-Latency Components.	VLSI Design	2000	DBLP DOI BibTeX RDF	variable latency units, data dependent computation, area-delay tradeoffs, High-level synthesis, performance optimization
1	Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana	A Technique for Identifying RTL and Gate-Level Correspondences. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	A framework for testing core-based systems-on-a-chip.	ICCAD	1999	DBLP BibTeX RDF
1	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits.	J. Electronic Testing	1998	DBLP DOI BibTeX RDF	controller resynthesis, test synthesis, high-level testing
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	TAO: regular expression based high-level testability analysis and optimization.	ITC	1998	DBLP DOI BibTeX RDF
1	Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey	Controller Resynthesis for Testability Enhancement of RTL Controller/Data path Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	Respecification, Synthesis for Testability, Don't Cares, High Level Testing
1	Srivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha	Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions.	ICCAD	1998	DBLP DOI BibTeX RDF

Publications of "Srivaths Ravi" ( http://dblp.L3S.de/Authors/Srivaths_Ravi )