|
|
|
|
Venues (Conferences, Journals, ...)
|
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 14 occurrences of 13 keywords
|
|
|
|
|
Results
Found 9 publication records. Showing 9 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
Understanding sources of ineffciency in general-purpose chips.  |
Commun. ACM  |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ofer Shacham, Omid Azizi, Megan Wachs, Stephen Richardson, Mark Horowitz |
Rethinking Digital Design: Why Design Must Change.  |
IEEE Micro  |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rehan Hameed, Wajahat Qadeer, Megan Wachs, Omid Azizi, Alex Solomatnikov, Benjamin C. Lee, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
Understanding sources of inefficiency in general-purpose chips.  |
ISCA  |
2010 |
DBLP DOI BibTeX RDF |
tensilica, energy efficiency, chip multiprocessor, customization, ASIC, h.264, high performance |
| 1 | Amin Firoozshahian, Alex Solomatnikov, Ofer Shacham, Zain Asgar, Stephen Richardson, Christos Kozyrakis, Mark Horowitz |
A memory system design framework: creating smart memories.  |
ISCA  |
2009 |
DBLP DOI BibTeX RDF |
memory access protocol, protocol controller, transactional memory, reconfigurable architecture, cache coherence, memory systems, multi-core processors, stream programming |
| 1 | Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz |
Using a configurable processor generator for computer architecture prototyping.  |
MICRO  |
2009 |
DBLP DOI BibTeX RDF |
computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design |
| 1 | Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz |
Verification of chip multiprocessor memory systems using a relaxed scoreboard.  |
MICRO  |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Richardson, Mahadevan Ganapathi |
Interprocedural analysis vs. procedure integration.  |
Inf. Process. Lett.  |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Richardson, Mahadevan Ganapathi |
Interprocedural Optimization: Experimental Results.  |
Softw., Pract. Exper.  |
1989 |
DBLP DOI BibTeX RDF |
|
| 1 | Stephen Richardson, Mahadevan Ganapathi |
Code Optimization Across Procedures.  |
IEEE Computer  |
1989 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #9 of 9 (100 per page; Change: )
|
|