Search results for "Stephen V. Kosonocky"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Stephen V. Kosonocky	Are you having fun yet?	IEEE Design & Test of Computers	2010	DBLP DOI BibTeX RDF
1	Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky	Keeping hot chips cool: are IC thermal problems hot air?	DAC	2008	DBLP DOI BibTeX RDF	VLSI design, thermal management, power dissipation
1	Zhenyu Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan	Multi-Dimensional Circuit and Micro-Architecture Level Optimization.	ISQED	2007	DBLP DOI BibTeX RDF
1	Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan	Structured and tuned array generation (STAG) for high-performance random logic.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	programmable logic arrays (PLAs), design automation
1	Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis	Early Power-Aware Design & Validation: Myth or Reality?	DAC	2007	DBLP DOI BibTeX RDF
1	Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky	Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies.	Integration	2005	DBLP DOI BibTeX RDF
1	Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin G. Stawiasz	Experimental measurement of a novel power gating structure with intermediate power saving mode.	ISLPED	2004	DBLP DOI BibTeX RDF	system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
1	Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky	Characterization of logic circuit techniques for high leakage CMOS technologies.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	monotonic logic, low power, leakage current
1	Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier	Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits.	IBM Journal of Research and Development	2003	DBLP DOI BibTeX RDF
1	Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban	Low-power circuits and technology for wireless digital systems.	IBM Journal of Research and Development	2003	DBLP DOI BibTeX RDF
1	Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel	Understanding and minimizing ground bounce during mode transition of power gating structures.	ISLPED	2003	DBLP DOI BibTeX RDF	system-on-a-chip (SOC) design, wake-up latency, clock gating, power gating, inductive noise, ground bounce
1	Alice Wang, Anantha Chandrakasan, Stephen V. Kosonocky	Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits.	ISVLSI	2002	DBLP DOI BibTeX RDF
1	Victor V. Zyuban, Stephen V. Kosonocky	Low power integrated scan-retention mechanism.	ISLPED	2002	DBLP DOI BibTeX RDF	balloon latch, data retention, low power, scan, leakage, latch, MTCMOS, subthreshold
1	W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design.	ISLPED	2001	DBLP DOI BibTeX RDF
1	Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown	Enchanced multi-threshold (MTCMOS) circuits using variable well bias.	ISLPED	2001	DBLP DOI BibTeX RDF	leakage control, low power digital circuit design, variable well bias, MTCMOS, multi-threshold
1	Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl	Interconnect-centric Array Architectures for Minimum SRAM Access Time.	ICCD	2001	DBLP BibTeX RDF
1	Stephen V. Kosonocky, Arthur A. Bright, Kevin W. Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David F. Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Benjamin D. Parker, T. V. Rajeevakumar, Kevin G. Stawiasz	Designing a Testable System on a Chip. (PDF / PS)	VTS	1998	DBLP DOI BibTeX RDF

Publications of "Stephen V. Kosonocky" ( http://dblp.L3S.de/Authors/Stephen_V._Kosonocky )