Search results for "Stephen W. Keckler"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron	A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors.	ACM Trans. Comput. Syst.	2012	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco	GPUs and the Future of Parallel Computing.	IEEE Micro	2011	DBLP DOI BibTeX RDF
1	Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu	Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees.	ISCA	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron	Energy-efficient mechanisms for managing thread context in throughput processors.	ISCA	2011	DBLP DOI BibTeX RDF
1	Jeffrey R. Diamond, Martin Burtscher, John D. McCalpin, Byoung-Do Kim, Stephen W. Keckler, James C. Browne	Evaluation and optimization of multicore performance bottlenecks in supercomputing applications.	ISPASS	2011	DBLP DOI BibTeX RDF
1	Mark Gebhart, Stephen W. Keckler, William J. Dally	A compile-time managed multi-level register file hierarchy.	MICRO	2011	DBLP DOI BibTeX RDF
1	Behnam Robatmili, Madhu Saravana Sibi Govindan, Doug Burger, Stephen W. Keckler	Exploiting criticality to reduce bottlenecks in distributed uniprocessors.	HPCA	2011	DBLP DOI BibTeX RDF
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Topology-Aware Quality-of-Service Support in Highly Integrated Chip Multiprocessors.	ISCA Workshops	2010	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, Luiz André Barroso (eds.)	36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA	ISCA	2009	DBLP BibTeX RDF
1	Nitya Ranganathan, Doug Burger, Stephen W. Keckler	Analysis of the TRIPS prototype block predictor.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger	End-to-end validation of architectural power models.	ISLPED	2009	DBLP DOI BibTeX RDF	architectural power models, measurement, validation
1	Mark Gebhart, Bertrand A. Maher, Katherine E. Coons, Jeffrey R. Diamond, Paul Gratz, Mario Marino, Nitya Ranganathan, Behnam Robatmili, Aaron Smith, James H. Burrill, Stephen W. Keckler, Doug Burger, Kathryn S. McKinley	An evaluation of the TRIPS computer system.	ASPLOS	2009	DBLP DOI BibTeX RDF	trips
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
1	Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu	Express Cube Topologies for on-Chip Interconnects.	HPCA	2009	DBLP DOI BibTeX RDF
1	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible core chip multiprocessors.	SIGARCH Computer Architecture News	2008	DBLP DOI BibTeX RDF
1	Franziska Roesner, Doug Burger, Stephen W. Keckler	Counting Dependence Predictors.	ISCA	2008	DBLP DOI BibTeX RDF
1	Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger	Multitasking workload scheduling on flexible-core chip multiprocessors.	PACT	2008	DBLP DOI BibTeX RDF	flexible cores, multitask scheduling, multicore architectures
1	Paul Gratz, Boris Grot, Stephen W. Keckler	Regional congestion awareness for load balance in networks-on-chip.	HPCA	2008	DBLP DOI BibTeX RDF
1	Jeffrey R. Diamond, Behnam Robatmili, Stephen W. Keckler, Robert A. van de Geijn, Kazushige Goto, Doug Burger	High performance dense linear algebra on a spatially distributed processor.	PPOPP	2008	DBLP DOI BibTeX RDF	gotoblas, grid processors, hybrid dataflow, matrix multiply, tile based architecture, instruction level parallelism, on-chip networks, dense linear algebra
1	John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh	Research Challenges for On-Chip Interconnection Networks.	IEEE Micro	2007	DBLP DOI BibTeX RDF	embedded systems, system on chip, network on chip, multicore architectures, on-chip interconnection networks
1	Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	On-Chip Interconnection Networks of the TRIPS Chip.	IEEE Micro	2007	DBLP DOI BibTeX RDF	communication, networking, distributed architectures, packet-switching networks, multicore architectures, on-chip interconnection networks
1	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distrib. Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
1	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
1	Heather Hanson, Stephen W. Keckler, Soraya Ghiasi, Karthick Rajamani, Freeman L. Rawson III, Juan Rubio	Thermal response to DVFS: analysis with an Intel Pentium M.	ISLPED	2007	DBLP DOI BibTeX RDF	thermal measurement, microprocessor, temperature, DVFS, thermal management
1	Paul Gratz, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of a Dynamically Routed Processor Operand Network.	NOCS	2007	DBLP DOI BibTeX RDF
1	Heather Hanson, Stephen W. Keckler, Karthick Rajamani, Soraya Ghiasi, Freeman L. Rawson III, Juan Rubio	Power, Performance, and Thermal Management for High-Performance Systems.	IPDPS	2007	DBLP DOI BibTeX RDF
1	Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler	Composable Lightweight Processors.	MICRO	2007	DBLP DOI BibTeX RDF
1	Jayaram Mudigonda, Harrick M. Vin, Stephen W. Keckler	Reconciling performance and programmability in networking systems.	SIGCOMM	2007	DBLP DOI BibTeX RDF	memoty bottleneck, multithreading, reconfigurable architectures, routers, data cache, processor architectures, packet processing
1	Michael T. Clark, Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler	The future of multi-core technologies.	CLUSTER	2007	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Xia Chen, Robert G. McDonald, Doug Burger, Stephen W. Keckler	Critical path analysis of the TRIPS architecture.	ISPASS	2006	DBLP DOI BibTeX RDF
1	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley	Dataflow Predication.	MICRO	2006	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.	MICRO	2006	DBLP DOI BibTeX RDF
1	Kartik K. Agaram, Stephen W. Keckler, Calvin Lin, Kathryn S. McKinley	Decomposing memory performance: data structures and phases.	ISMM	2006	DBLP DOI BibTeX RDF	CPU2000, DTrack, simulation, data structure, phase, SPEC
1	Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger	Implementation and Evaluation of On-Chip Network Architectures.	ICCD	2006	DBLP BibTeX RDF
1	Simha Sethumadhavan, Robert G. McDonald, Rajagopalan Desikan, Doug Burger, Stephen W. Keckler	Design and Implementation of the TRIPS Primary Memory System.	ICCD	2006	DBLP BibTeX RDF
1	Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA substrate for flexible CMP cache sharing.	ICS	2005	DBLP DOI BibTeX RDF	cache sharing, non-uniform cache architecture, chip-multiprocessor
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore	TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.	TACO	2004	DBLP DOI BibTeX RDF	scalable and high-performance computing, Computer architecture, configurable computing
1	Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler	Scalable Hardware Memory Disambiguation for High-ILP Processors.	IEEE Micro	2004	DBLP DOI BibTeX RDF
1	Doug Burger, Stephen W. Keckler, Kathryn S. McKinley, Michael Dahlin, Lizy Kurian John, Calvin Lin, Charles R. Moore, James H. Burrill, Robert G. McDonald, William Yode	Scaling to the End of Silicon with EDGE Architectures.	IEEE Computer	2004	DBLP DOI BibTeX RDF
1	Doug Burger, Todd M. Austin, Stephen W. Keckler	Recent extensions to the SimpleScalar tool suite.	SIGMETRICS Performance Evaluation Review	2004	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Sundeep K. Kushwaha, Doug Burger, Kathryn S. McKinley, Calvin Lin, Stephen W. Keckler	Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures.	IEEE PACT	2004	DBLP DOI BibTeX RDF
1	Rajagopalan Desikan, Simha Sethumadhavan, Doug Burger, Stephen W. Keckler	Scalable selective re-execution for EDGE architectures.	ASPLOS	2004	DBLP DOI BibTeX RDF	EDGE architectures, load-store dependence prediction, mis-speculation recovery, selective re-execution, selective replay, speculative dataflow machines
1	Changkyu Kim, Doug Burger, Stephen W. Keckler	Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore	Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture.	IEEE Micro	2003	DBLP DOI BibTeX RDF
1	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static energy reduction techniques for microprocessor caches.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore	Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. (PDF / PS)	ISCA	2003	DBLP DOI BibTeX RDF
1	Karthik Natarajan, Heather Hanson, Stephen W. Keckler, Charles R. Moore, Doug Burger	Microprocessor pipeline energy analysis.	ISLPED	2003	DBLP DOI BibTeX RDF	alpha 21264, over-provisioning, power, energy, speculation
1	Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler	Scalable Hardware Memory Disambiguation for High ILP Processors.	MICRO	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Stephen W. Keckler, William R. Mark, Doug Burger	Universal Mechanisms for Data-Parallel Architectures.	MICRO	2003	DBLP DOI BibTeX RDF
1	Karthikeyan Sankaralingam, Vincent Ajay Singh, Stephen W. Keckler, Doug Burger	Routed Inter-ALU Networks for ILP Scalability and Performance.	ICCD	2003	DBLP DOI BibTeX RDF
1	Premkishore Shivakumar, Stephen W. Keckler, Charles R. Moore, Doug Burger	Exploiting Microarchitectural Redundancy For Defect Tolerance.	ICCD	2003	DBLP DOI BibTeX RDF
1	Rajagopalan Desikan, Doug Burger, Stephen W. Keckler, José-Lorenzo Cruz, Fernando Latorre, Antonio González, Mateo Valero	Errata on "Measuring Experimental Error in Microprocessor Simulation".	SIGARCH Computer Architecture News	2002	DBLP DOI BibTeX RDF
1	M. S. Hrishikesh, Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, Norman P. Jouppi, Keith I. Farkas	The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays. (PDF / PS)	ISCA	2002	DBLP DOI BibTeX RDF	instruction queue clock rate, Pipelining
1	Changkyu Kim, Doug Burger, Stephen W. Keckler	An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches.	ASPLOS	2002	DBLP DOI BibTeX RDF
1	Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler, Doug Burger, Lorenzo Alvisi	Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic.	DSN	2002	DBLP DOI BibTeX RDF
1	Jaehyuk Huh, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
1	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
1	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static Energy Reduction Techniques for Microprocessor Caches.	ICCD	2001	DBLP BibTeX RDF
1	Vikas Agarwal, M. S. Hrishikesh, Stephen W. Keckler, Doug Burger	Clock rate versus IPC: the end of the road for conventional microarchitectures.	ISCA	2000	DBLP DOI BibTeX RDF
1	Daniel A. Jiménez, Stephen W. Keckler, Calvin Lin	The impact of delay on the design of branch predictors.	MICRO	2000	DBLP DOI BibTeX RDF
1	Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang	Processor Mechanisms for Software Shared Memory.	ISHPC	2000	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally	Concurrent Event Handling through Multithreading.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF
1	Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang	An Efficient, Protected Message Interface.	IEEE Computer	1998	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee	Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor.	ISCA	1998	DBLP DOI BibTeX RDF
1	Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee	The M-machine multicomputer.	International Journal of Parallel Programming	1997	DBLP DOI BibTeX RDF
1	Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee	The M-Machine multicomputer.	MICRO	1995	DBLP DOI BibTeX RDF
1	Nicholas P. Carter, Stephen W. Keckler, William J. Dally	Hardware Support for Fast Capability-based Addressing.	ASPLOS	1994	DBLP DOI BibTeX RDF
1	Stephen W. Keckler, William J. Dally	Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism.	ISCA	1992	DBLP DOI BibTeX RDF

Publications of "Stephen W. Keckler" ( http://dblp.L3S.de/Authors/Stephen_W._Keckler )