Search results for "Steve Furber"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Francesco Galluppi, Sergio Davies, Alexander D. Rast, Thomas Sharp, Luis A. Plana, Steve Furber	A hierachical configuration system for a massively parallel neural hardware platform.	Conf. Computing Frontiers	2012	DBLP DOI BibTeX RDF
1	Mukaram M. Khan, Alexander D. Rast, Javier Navaridas, X. Jin, Luis A. Plana, Mikel Luján, Steve Temple, Cameron Patterson, D. Richards, John V. Woods, José Miguel-Alonso, Stephen B. Furber	Event-driven configuration of a neural network CMP system over an homogeneous interconnect fabric.	Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Michael Merrett, P. Asenov, Yangang Wang, Mark Zwolinski, Dave Reid, Campbell Millar, Scott Roy, Zhenyu Liu, Stephen B. Furber, Asen Asenov	Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis.	DATE	2011	DBLP DOI BibTeX RDF
1	Stephen B. Furber	Biologically-inspired massively-parallel architectures - Computing beyond a million processors.	DATE	2011	DBLP BibTeX RDF
1	Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis Plana, Cameron Patterson, Thomas Sharp, David R. Lester, Steve Furber	Concurrent heterogeneous neural model simulation on real-time neuromimetic hardware.	Neural Networks	2011	DBLP DOI BibTeX RDF
1	Luis A. Plana, David M. Clark, Simon Davidson, Steve Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge	SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip.	JETC	2011	DBLP DOI BibTeX RDF
1	Martin Grymel, Steve Furber	A Novel Programmable Parallel CRC Circuit.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	David R. Lester, Steve Furber	SpiNNaker: Distributed Computer Engineering for Neuromorphics.	WIRN	2011	DBLP DOI BibTeX RDF
1	Thomas Sharp, Luis A. Plana, Francesco Galluppi, Steve Furber	Event-Driven Simulation of Arbitrary Spiking Neural Networks on SpiNNaker.	ICONIP	2011	DBLP DOI BibTeX RDF
1	Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber	Maintaining real-time synchrony on SpiNNaker.	Conf. Computing Frontiers	2011	DBLP DOI BibTeX RDF
1	Steve Furber	Biologically-Inspired Massively-Parallel Architectures: A Reconfigurable Neural Modelling Platform.	ARC	2011	DBLP DOI BibTeX RDF
1	Francesco Galluppi, Steve Furber	Representing and decoding rank order codes using polychronization in a network of spiking neurons.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Thomas Sharp, Cameron Patterson, Steve Furber	Distributed configuration of massively-parallel simulation on SpiNNaker neuromorphic hardware.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Sergio Davies, Alexander D. Rast, Francesco Galluppi, Steve Furber	A forecast-based biologically-plausible STDP learning rule.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Alexander D. Rast, Francesco Galluppi, Sergio Davies, Luis A. Plana, Thomas Sharp, Steve Furber	An event-driven model for the SpiNNaker virtual synaptic channel.	IJCNN	2011	DBLP DOI BibTeX RDF
1	Basabdatta Sen Bhattacharya, Stephen B. Furber	Biologically inspired means for rank-order encoding images: a quantitative analysis.	IEEE Transactions on Neural Networks	2010	DBLP DOI BibTeX RDF
1	Javier Navaridas, Luis A. Plana, José Miguel-Alonso, Mikel Luján, Stephen B. Furber	SpiNNaker: impact of traffic locality, causality and burstiness on the performance of the interconnection network.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	power-efficient architectures, performance evaluation, interconnection networks, system-on-chip, real-time applications, spiking neural networks, traffic characterization, massively parallel systems
1	Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber	Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	universal neural processor, asynchronous, event-driven
1	Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber	Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware.	ISPDC	2010	DBLP DOI BibTeX RDF	SpiNNaker, parallel, mapping, backpropagation, perceptron
1	Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve Furber	Modeling Spiking Neural Networks on SpiNNaker.	Computing in Science and Engineering	2010	DBLP DOI BibTeX RDF	multicore system-on-chip, globally asynchronous locally synchronous design, spiking neural net simulation, biological real-time computing, Massively parallel computing, neural modeling
1	Jian Wu, Steve Furber	A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture.	Comput. J.	2010	DBLP DOI BibTeX RDF
1	Francesco Galluppi, Alexander D. Rast, Sergio Davies, Steve Furber	A General-Purpose Model Translation System for a Universal Neural Chip.	ICONIP	2010	DBLP DOI BibTeX RDF
1	Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve Furber	Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	mlp, spinnaker, parallel, mapping, pipeline, backpropagation
1	Andrew D. Brown, Steve Furber, Jeff S. Reeve, Peter R. Wilson, Mark Zwolinski, John E. Chad, Luis A. Plana, David R. Lester	A communication infrastructure for a million processor machine.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	multi-core, self-organisation
1	Xin Jin, Alexander D. Rast, Francesco Galluppi, Sergio Davies, Steve Furber	Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Xin Jin, Francesco Galluppi, Cameron Patterson, Alexander D. Rast, Sergio Davies, Steve Temple, Steve Furber	Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Alexander D. Rast, Francesco Galluppi, Xin Jin, Steve Furber	The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip.	IJCNN	2010	DBLP DOI BibTeX RDF
1	Shufan Yang, Stephen B. Furber, Yebin Shi, Luis A. Plana	A Token-Managed Admission Control System for QoS Provision on a Best-Effort GALS Interconnect.	Fundam. Inform.	2009	DBLP DOI BibTeX RDF
1	Stephen B. Furber, Andrew D. Brown	Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors.	ACSD	2009	DBLP DOI BibTeX RDF	neural networks, fault-tolerance, Massively-parallel
1	Jim D. Garside, Stephen B. Furber, Steve Temple, Viv Woods	The Amulet chips: Architectural development for asynchronous microprocessors.	ICECS	2009	DBLP DOI BibTeX RDF
1	Shufan Yang, Stephen B. Furber, Luis A. Plana	Adaptive admission control on the SpiNNaker MPSoC.	SoCC	2009	DBLP DOI BibTeX RDF
1	Xin Jin, Alexander D. Rast, Francesco Galluppi, Muhammad Mukaram Khan, Steve Furber	Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor.	ICONIP	2009	DBLP DOI BibTeX RDF
1	Javier Navaridas, Mikel Luján, José Miguel-Alonso, Luis A. Plana, Steve Furber	Understanding the interconnection network of SpiNNaker.	ICS	2009	DBLP DOI BibTeX RDF	biologically inspired architecture, performance evaluation, fault tolerance, interconnection networks, systems on chip, real-time applications, spiking neurons, massively parallel architecture, analytical evaluation
1	Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steve Furber	Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric.	ISPDC	2009	DBLP DOI BibTeX RDF	Multi-CMP Configuration, Neural Networks, Fault-tolerance, Embedded Systems, Chip Multiprocessor, Real-time Application, Massively Parallel Computing
1	Alexander D. Rast, Stephen R. Welbourne, Xin Jin, Steve Furber	Optimal connectivity in hardware-targetted MLP networks.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Alexander D. Rast, Mukaram M. Khan, Xin Jin, Luis A. Plana, Steve Furber	A universal abstract-time platform for real-time neural networks.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Basabdatta Sen Bhattacharya, Steve Furber	Evaluating rank-order code performance using a biologically-derived retinal model.	IJCNN	2009	DBLP DOI BibTeX RDF
1	Alexander D. Rast, Shufan Yang, Muhammad Mukaram Khan, Stephen B. Furber	Virtual synaptic interconnect using an asynchronous network-on-chip.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, Eustace Painkras, Stephen B. Furber	SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Xin Jin, Stephen B. Furber, John V. Woods	Efficient modelling of spiking neural networks on a scalable chip multiprocessor.	IJCNN	2008	DBLP DOI BibTeX RDF
1	Steve Furber	The Future of Computer Technology and its Implications for the Computer Industry.	Comput. J.	2008	DBLP DOI BibTeX RDF
1	Steve Furber, Steve Temple	Neural Systems Engineering.	Computational Intelligence: A Compendium	2008	DBLP DOI BibTeX RDF
1	Shufan Yang, Steve Furber, Yebin Shi, Luis A. Plana	An admission control system for QoS provision on a best-effort GALS interconnect.	ACSD	2008	DBLP DOI BibTeX RDF
1	Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu	An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator.	NOCS	2008	DBLP DOI BibTeX RDF	Synchonizer, source-address routing, GALS, Bandwidth aggregation
1	Alexander D. Rast, Xin Jin, Muhammad Mukaram Khan, Steve Furber	The Deferred Event Model for Hardware-Oriented Spiking Neural Networks.	ICONIP	2008	DBLP DOI BibTeX RDF
1	Andrew D. Brown, David R. Lester, Luis A. Plana, Steve Furber, Peter R. Wilson	SpiNNaker: The Design Automation Problem.	ICONIP	2008	DBLP DOI BibTeX RDF
1	Stephen B. Furber, G. Brown, Joy Bose, J. Mike Cumpstey, P. Marshall, Jonathan L. Shapiro	Sparse Distributed Memory Using Rank-Order Neural Codes.	IEEE Transactions on Neural Networks	2007	DBLP DOI BibTeX RDF
1	Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang	A GALS Infrastructure for a Massively Parallel Multiprocessor.	IEEE Design & Test of Computers	2007	DBLP DOI BibTeX RDF	massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
1	Jo C. Ebergen, Steve Furber, Arash Saifhashemi	Notes On Pulse Signaling.	ASYNC	2007	DBLP DOI BibTeX RDF
1	Joy Bose, Stephen B. Furber, Jonathan L. Shapiro	An associative memory for the on-line recognition and prediction of temporal sequences	CoRR	2006	DBLP BibTeX RDF
1	Stephen B. Furber, Steve Temple, Andrew D. Brown	On-chip and inter-chip networks for modeling large-scale neural systems.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Yijun Liu, Steve Furber, Zhenkun Li	The Design of a Dataflow Coprocessor for Low Power Embedded Hierarchical Processing.	PATMOS	2006	DBLP DOI BibTeX RDF
1	Steve Furber	Living with Failure: Lessons from Nature?	European Test Symposium	2006	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	A Low Power Embedded Dataflow Coprocessor.	ISVLSI	2005	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.	PATMOS	2005	DBLP DOI BibTeX RDF
1	Joy Bose, Stephen B. Furber, Jonathan L. Shapiro	A System for Transmitting a Coherent Burst of Activity Through a Network of Spiking Neurons.	WIRN/NAIS	2005	DBLP DOI BibTeX RDF
1	Joy Bose, Stephen B. Furber, Jonathan L. Shapiro	A Spiking Neural Sparse Distributed Memory Implementation for Learning and Predicting Temporal Sequences.	ICANN	2005	DBLP DOI BibTeX RDF
1	Alexandre Yakovlev, Stephen B. Furber, René Krenz, Alexandre V. Bystrov	Design and Analysis of a Self-Timed Duplex Communication System.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
1	Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple	Sparse distributed memory using N-of-M codes.	Neural Networks	2004	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	Minimizing the Power Consumption of an Asynchronous Multiplier.	PATMOS	2004	DBLP DOI BibTeX RDF
1	Yijun Liu, Stephen B. Furber	The design of a low power asynchronous multiplier.	ISLPED	2004	DBLP DOI BibTeX RDF	Booth's algorithm, low power, benchmark, multiplier, asynchronous logic
1	W. J. Bainbridge, Luis A. Plana, Stephen B. Furber	The Design and Test of a Smartcard Chip Using a CHAIN Self-Timed Network-on-Chip.	DATE	2004	DBLP DOI BibTeX RDF
1	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An asynchronous copy-back cache architecture.	Microprocessors and Microsystems	2003	DBLP DOI BibTeX RDF
1	T. Felicijan, Stephen B. Furber	An asynchronous ternary logic signaling system.	IEEE Trans. VLSI Syst.	2003	DBLP DOI BibTeX RDF
1	W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber	Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Z. C. Yu, Stephen B. Furber, Luis A. Plana	An Investigation into the Security of Self-Timed Circuits.	ASYNC	2003	DBLP DOI BibTeX RDF
1	Steve Furber	Editorial.	Microprocessors and Microsystems	2003	DBLP DOI BibTeX RDF
1	John Bainbridge, Stephen B. Furber	Chain: A Delay-Insensitive Chip Area Interconnect.	IEEE Micro	2002	DBLP DOI BibTeX RDF
1	Stephen B. Furber	Validating the AMULET Microprocessors.	Comput. J.	2002	DBLP DOI BibTeX RDF
1	Daranee Hormdee, Jim D. Garside, Stephen B. Furber	An Asynchronous Victim Cache.	DSD	2002	DBLP DOI BibTeX RDF	copy-back cache architecture, asynchronous design, victim cache
1	Stephen B. Furber, Aristides Efthymiou, Jim D. Garside, David W. Lloyd, Mike J. G. Lewis, Steve Temple	Power Management in the Amulet Microprocessors.	IEEE Design & Test of Computers	2001	DBLP DOI BibTeX RDF
1	P. A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber	A Low-Power Self-Timed Viterbi Decoder.	ASYNC	2001	DBLP DOI BibTeX RDF
1	W. J. Bainbridge, Stephen B. Furber	Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.	ASYNC	2001	DBLP DOI BibTeX RDF
1	Jim D. Garside, W. J. Bainbridge, Andrew Bardsley, David M. Clark, David A. Edwards, Stephen B. Furber, David W. Lloyd, S. Mohammadi, J. S. Pepper, Steve Temple, John V. Woods, Jianwei Liu, O. Petli	AMULET3i - An Asynchronous System-on-Chip. (PDF / PS)	ASYNC	2000	DBLP DOI BibTeX RDF
1	Stephen B. Furber, David A. Edwards, Jim D. Garside	AMULET3: A 100 MIPS Asynchronous Embedded Processor. (PDF / PS)	ICCD	2000	DBLP DOI BibTeX RDF
1	Jim D. Garside, Stephen B. Furber, S.-H. Chung	AMULET3 Revealed.	ASYNC	1999	DBLP DOI BibTeX RDF
1	W. J. Bainbridge, Stephen B. Furber	Asynchronous Macrocell Interconnect using MARBLE.	ASYNC	1998	DBLP DOI BibTeX RDF	Macrocell Bus, VLSI, Interconnect, Asynchronous
1	Sun-Yen Tan, Stephen B. Furber, Wen-Fang Yen	The Design of an Asynchronous VHDL Synthesizer.	DATE	1998	DBLP DOI BibTeX RDF	Synthesis, VHDL, Asynchronous
1	Philip Endecott, Stephen B. Furber	Modelling and Simulation of Asynchronous Systems Using the LARD Hardware Description Language.	ESM	1998	DBLP BibTeX RDF
1	John V. Woods, P. Day, Stephen B. Furber, Jim D. Garside, N. C. Paver, Steve Temple	AMULET1: A Asynchronous ARM Microprocessor.	IEEE Trans. Computers	1997	DBLP DOI BibTeX RDF
1	O. A. Petlin, Stephen B. Furber	Built-In Self-Testing of Micropipelines.	ASYNC	1997	DBLP DOI BibTeX RDF	Built-in self-test, Design for test, Asynchronous design, Micropipelines
1	Stephen B. Furber, Jim D. Garside, Steve Temple, Jianwei Liu, P. Day, N. C. Paver	AMULET2e: An Asynchronous Embedded Controller.	ASYNC	1997	DBLP DOI BibTeX RDF	Low power, Microprocessors, Asynchronous design, Embedded control
1	Stephen B. Furber, P. Day	Four-phase micropipeline latch control circuits.	IEEE Trans. VLSI Syst.	1996	DBLP DOI BibTeX RDF
1	Stephen B. Furber	The Return of Asynchronous Logic.	ITC	1996	DBLP DOI BibTeX RDF
1	O. A. Petlin, Stephen B. Furber	Scan testing of asynchronous sequential circuits.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	micropipeline design style, combinational block, state holding elements, standard test generation techniques, VLSI, logic testing, delays, integrated circuit testing, logic design, sequential circuits, asynchronous circuits, integrated logic circuits, delay faults, boundary scan testing, scan testing, single stuck-at faults, asynchronous sequential logic, asynchronous sequential circuits
1	O. A. Petlin, Stephen B. Furber	Scan testing of micropipelines.	VTS	1995	DBLP DOI BibTeX RDF	asynchronous VLSI circuit design, AMULET1 microprocessor, scan test technique, data processing blocks, combinational processing logic, state holding elements, test generation techniques, VLSI, logic testing, delays, integrated circuit testing, design for testability, logic design, asynchronous circuits, fault location, integrated circuit design, microprocessor chips, delay faults, boundary scan testing, computer testing, test patterns, single stuck-at faults, micropipelines
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods	AMULET1: A Micropipelined ARM.	COMPCON	1994	DBLP BibTeX RDF
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, Steve Temple, John V. Woods	The Design and Evaluation of an Asynchronous Microprocessor.	ICCD	1994	DBLP BibTeX RDF
1	Stephen B. Furber, P. Day, Jim D. Garside, N. C. Paver, John V. Woods	A micropipelined ARM.	VLSI	1993	DBLP BibTeX RDF
1	Stephen B. Furber, Martyn Edwards (eds.)	Asynchronous Design Methodologies, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, Manchester, UK, 31 March - 2 April, 1993	Asynchronous Design Methodologies	1993	DBLP BibTeX RDF
1	N. C. Paver, P. Day, Stephen B. Furber, Jim D. Garside, John V. Woods	Register Locking in an Asynchronous Microprocessor.	ICCD	1992	DBLP BibTeX RDF

Publications of Steve Furber Stephen B. Furber ( http://dblp.L3S.de/Authors/Steve_Furber )