Search results for "Steven Derrien"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	System-Level Synthesis for Wireless Sensor Node Controllers: A Complete Design Flow.	ACM Trans. Design Autom. Electr. Syst.	2012	DBLP DOI BibTeX RDF
1	Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien	A Polynomial Based Approach to Wakeup Time and Energy Estimation in Power-Gated Logic Clusters.	J. Low Power Electronics	2011	DBLP BibTeX RDF
1	V. Basupalli, Tomofumi Yuki, Sanjay V. Rajopadhye, Antoine Morvan, Steven Derrien, Patrice Quinton, David Wonnacott	ompVerify: Polyhedral Analysis for the OpenMP Programmer.	IWOMP	2011	DBLP DOI BibTeX RDF
1	Antoine Morvan, Steven Derrien, Patrice Quinton	Efficient nested loop pipelining in high level synthesis using polyhedral bubble insertion.	FPT	2011	DBLP DOI BibTeX RDF
1	Antoine Floch, Tomofumi Yuki, Clement Guy, Steven Derrien, Benoît Combemale, Sanjay V. Rajopadhye, Robert B. France	Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far?	MoDELS	2011	DBLP DOI BibTeX RDF
1	Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien	Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters.	VLSI Design	2011	DBLP DOI BibTeX RDF
1	Alexandre Cornu, Steven Derrien, Dominique Lavenier	HLS Tools for FPGA: Faster Development with Better Performance.	ARC	2011	DBLP DOI BibTeX RDF
1	Steven Derrien, Patrice Quinton	Hardware Acceleration of HMMER on FPGAs.	Signal Processing Systems	2010	DBLP DOI BibTeX RDF
1	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes.	DSD	2010	DBLP DOI BibTeX RDF
1	Naeem Abbas, Steven Derrien, Sanjay V. Rajopadhye, Patrice Quinton	Accelerating HMMER on FPGA using parallel prefixes and reductions.	FPT	2010	DBLP DOI BibTeX RDF
1	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	A complete design-flow for the generation of ultra low-power WSN node architectures based on micro-tasking.	DAC	2010	DBLP DOI BibTeX RDF	WSN node, hardware specialization, microcoded architecture, low-power design
1	Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys	Ultra Low-power FSM for Control Oriented Applications.	ISCAS	2009	DBLP DOI BibTeX RDF
1	Steven Derrien, Alexandru Turjan, Claudiu Zissulescu, Bart Kienhuis, Ed F. Deprettere	Deriving efficient control in Process Networks with Compaan/Laura.	IJES	2008	DBLP DOI BibTeX RDF
1	Steven Derrien, Patrice Quinton	Parallelizing HMMER for Hardware Acceleration on FPGAs.	ASAP	2007	DBLP DOI BibTeX RDF
1	Rayan Chikhi, Steven Derrien, Auguste Noumsi, Patrice Quinton	Combining Flash Memory and FPGAs to Efficiently Implement a Massively Parallel Algorithm for Content-Based Image Retrieval.	ARC	2007	DBLP DOI BibTeX RDF
1	Auguste Noumsi, Steven Derrien, Patrice Quinton	Acceleration of a content-based image-retrieval application on the RDISK cluster.	IPDPS	2006	DBLP DOI BibTeX RDF
1	Stéphane Guyetant, Mathieu Giraud, Ludovic L'Hours, Steven Derrien, Stéphane Rubini, Dominique Lavenier, Frédéric Raimbault	Cluster of re-configurable nodes for scanning large genomic banks.	Parallel Computing	2005	DBLP DOI BibTeX RDF
1	Alain Darte, Steven Derrien, Tanguy Risset	Hardware/Software Interface for Multi-Dimensional Processor Arrays.	ASAP	2005	DBLP DOI BibTeX RDF
1	Dominique Lavenier, Stéphane Guyetant, Steven Derrien, Stéphane Rubini	A Reconfigurable Parallel Disk System for Filtering Genomic Banks.	Engineering of Reconfigurable Systems and Algorithms	2003	DBLP BibTeX RDF
1	Sanjay V. Rajopadhye, Steven Derrien	Energy/Power Estimation of Regular Processor Arrays.	ISSS	2002	DBLP DOI BibTeX RDF	processor array partitioning, design space exploration, power estimation, programmable logic
1	Steven Derrien, Sanjay V. Rajopadhye	Loop Tiling for Reconfigurable Accelerators.	FPL	2001	DBLP DOI BibTeX RDF
1	Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay	Combined instruction and loop parallelism in array synthesis for FPGAs.	ISSS	2001	DBLP BibTeX RDF
1	Steven Derrien, Sanjay V. Rajopadhye, Susmita Sur-Kolay	Optimal Partitioning for FPGA Based Regular Array Implementations.	PARELEC	2000	DBLP DOI BibTeX RDF
1	Steven Derrien, Kurt Konolige	Approximating a Single Viewpoint in Panoramic Imaging Devices.	ICRA	2000	DBLP BibTeX RDF
1	Steven Derrien, Tanguy Risset	Interfacing compiled FPGA programs: the MMAlpha approach.	PDPTA	2000	DBLP BibTeX RDF
1	Steven Derrien, Sanjay V. Rajopadhye	FCCMS and the Memory Wall.	FCCM	2000	DBLP DOI BibTeX RDF

Publications of "Steven Derrien" ( http://dblp.L3S.de/Authors/Steven_Derrien )