Search results for "Subhasish Mitra"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Hyungmin Cho, Larkhoon Leem, Subhasish Mitra	ERSA: Error Resilient System Architecture for Probabilistic Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Jie Zhang, Albert Lin, Nishant Patil, Hai Wei, Lan Wei, H.-S. Philip Wong, Subhasish Mitra	Carbon Nanotube Robust Digital VLSI.	IEEE Trans. on CAD of Integrated Circuits and Systems	2012	DBLP DOI BibTeX RDF
1	Subhasish Mitra, David Lin, Nagib Hakim, Donald S. Gardner	Bug localization techniques for effective post-silicon validation.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chen Chen, W. Scott Lee, J. Provine, Soogine Chong, Roozbeh Parsa, Dae Sung Lee, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing.	ASP-DAC	2012	DBLP DOI BibTeX RDF
1	Chen Chen, W. Scott Lee, Roozbeh Parsa, Soogine Chong, J. Provine, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique.	DATE	2012	DBLP BibTeX RDF
1	Igor Loi, Federico Angiolini, Shinobu Fujita, Subhasish Mitra, Luca Benini	Characterization and Implementation of Fault-Tolerant Vertical Links for 3-D Networks-on-Chip.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Jie Zhang, Nishant Patil, Arash Hazeghi, H.-S. Philip Wong, Subhasish Mitra	Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra	Self-Tuning for Maximized Lifetime Energy-Efficiency in the Presence of Circuit Aging.	IEEE Trans. on CAD of Integrated Circuits and Systems	2011	DBLP DOI BibTeX RDF
1	John K. Ousterhout, Parag Agrawal, David Erickson, Christos Kozyrakis, Jacob Leverich, David Mazières, Subhasish Mitra, Aravind Narayanan, Diego Ongaro, Guru M. Parulkar, Mendel Rosenblum, Stephen M. Rumble, Eric Stratmann, Ryan Stutsman	The case for RAMCloud.	Commun. ACM	2011	DBLP DOI BibTeX RDF
1	Chen Dong, Chen Chen, Subhasish Mitra, Deming Chen	Architecture and performance evaluation of 3D CMOS-NEM FPGA.	SLIP	2011	DBLP DOI BibTeX RDF
1	Hai Wei, Jie Zhang, Lan Wei, Nishant Patil, Albert Lin, Max M. Shulaker, Hong-Yu Chen, H.-S. Philip Wong, Subhasish Mitra	Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated.	ICCAD	2011	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Subhasish Mitra	Post-silicon bug localization for processors using IFRA.	Commun. ACM	2010	DBLP DOI BibTeX RDF
1	Ted Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, Subhasish Mitra	QED: Quick Error Detection tests for effective post-silicon validation.	ITC	2010	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Anne Bracy, Hong Wang 0003, Subhasish Mitra	BLoG: post-silicon bug localization in processors using bug localization graphs.	DAC	2010	DBLP DOI BibTeX RDF	IFRA, BLoG, silicon debug, post-silicon validation
1	Subhasish Mitra, Sanjit A. Seshia, Nicola Nicolici	Post-silicon validation opportunities, challenges and recent advances.	DAC	2010	DBLP DOI BibTeX RDF	post-silicon validation
1	Jie Zhang, Shashikanth Bobba, Nishant Patil, Albert Lin, H.-S. Philip Wong, Giovanni De Micheli, Subhasish Mitra	Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.	DAC	2010	DBLP DOI BibTeX RDF	CNT correlation, carbon nanotube, yield optimization, CNT
1	Yanjing Li, Onur Mutlu, Donald S. Gardner, Subhasish Mitra	Concurrent autonomous self-test for uncore components in system-on-chips.	VTS	2010	DBLP DOI BibTeX RDF
1	Young Moon Kim, Tze Wee Chen, Y. Kameda, M. Mizuno, Subhasish Mitra	Gate-oxide early-life failure identification using delay shifts.	VTS	2010	DBLP DOI BibTeX RDF
1	Chen Chen, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra	Efficient FPGAs using nanoelectromechanical relays.	FPGA	2010	DBLP DOI BibTeX RDF	CMOS-NEM FPGA, nanoelectromechanical relay
1	Subhasish Mitra	Robust System Design.	VLSI Design	2010	DBLP DOI BibTeX RDF	Robust systems, IFRA, BISER, Built-In Soft Error Resilience, Circuit Failure Prediction, On-line Self-Test, Reliability, Validation, aging, soft errors, post-silicon validation
1	Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. Jacobson, Subhasish Mitra	ERSA: Error Resilient System Architecture for probabilistic applications.	DATE	2010	DBLP BibTeX RDF
1	Subhasish Mitra, Kevin Brelsford, Pia N. Sanda	Cross-layer resilience challenges: Metrics and optimization.	DATE	2010	DBLP BibTeX RDF
1	Yashodhan Kanoria, Subhasish Mitra, Andrea Montanari	Statistical static timing analysis using Markov chain Monte Carlo.	DATE	2010	DBLP BibTeX RDF
1	Evelyn Mintarno, Joëlle Skaf, Rui Zheng, Jyothi Velamala, Yu Cao, Stephen P. Boyd, Robert W. Dutton, Subhasish Mitra	Optimized self-tuning for circuit aging.	DATE	2010	DBLP BibTeX RDF
1	Jie Zhang, Nishant Patil, Albert Lin, H.-S. Philip Wong, Subhasish Mitra	Carbon nanotube circuits: Living with imperfections and variations.	DATE	2010	DBLP BibTeX RDF
1	Larkhoon Leem, Hyungmin Cho, Hsiao-Heng Lee, Young Moon Kim, Yanjing Li, Subhasish Mitra	Cross-layer error resilience for robust systems.	ICCAD	2010	DBLP DOI BibTeX RDF
1	Jie Zhang, Nishant Patil, Subhasish Mitra	Probabilistic Analysis and Design of Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Ted Hong, Subhasish Mitra	Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA).	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	John K. Ousterhout, Parag Agrawal, David Erickson, Christos Kozyrakis, Jacob Leverich, David Mazières, Subhasish Mitra, Aravind Narayanan, Guru M. Parulkar, Mendel Rosenblum, Stephen M. Rumble, Eric Stratmann, Ryan Stutsman	The case for RAMClouds: scalable high-performance storage entirely in DRAM.	Operating Systems Review	2009	DBLP DOI BibTeX RDF
1	Yanjing Li, Young Moon Kim, Evelyn Mintarno, Donald S. Gardner, Subhasish Mitra	Overcoming Early-Life Failure and Aging for Robust Systems.	IEEE Design & Test of Computers	2009	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Subhasish Mitra	IFRA: Post-silicon bug localization in processors.	HLDVT	2009	DBLP DOI BibTeX RDF
1	Rui Zheng, Jyothi Velamala, Vijay Reddy, Varsha Balakrishnan, Evelyn Mintarno, Subhasish Mitra, Srikanth Krishnan, Yu Cao	Circuit aging prediction for low-power operation.	CICC	2009	DBLP DOI BibTeX RDF
1	Nishant Patil, Albert Lin, Jie Zhang, H.-S. Philip Wong, Subhasish Mitra	Digital VLSI logic technology using Carbon Nanotube FETs: frequently asked questions.	DAC	2009	DBLP DOI BibTeX RDF	CNFET, carbon nanotube transistor, carbon nanotubes
1	Jie Zhang, Nishant Patil, Arash Hazeghi, Subhasish Mitra	Carbon nanotube circuits in the presence of carbon nanotube density variations.	DAC	2009	DBLP DOI BibTeX RDF	CNT correlation, CNT density variation, carbon nanotube, CNT
1	A. Hakan Baba, Subhasish Mitra	Testing for Transistor Aging.	VTS	2009	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei	Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors.	DATE	2009	DBLP BibTeX RDF
1	Yanjing Li, Onur Mutlu, Subhasish Mitra	Operating system scheduling for efficient online self-test in robust systems.	ICCAD	2009	DBLP BibTeX RDF
1	Soogine Chong, Kerem Akarvardar, Roozbeh Parsa, Jun-Bo Yoon, Roger T. Howe, Subhasish Mitra, H.-S. Philip Wong	Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage.	ICCAD	2009	DBLP BibTeX RDF
1	Nishant Patil, Subhasish Mitra	Imperfection-immune Carbon Nanotube digital VLSI.	ICCD	2009	DBLP DOI BibTeX RDF
1	Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra	Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits.	IEEE Trans. on CAD of Integrated Circuits and Systems	2008	DBLP DOI BibTeX RDF
1	Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey	The Search for Alternative Computational Paradigms.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF
1	Rohit Kapur, Subhasish Mitra, Thomas W. Williams	Historical Perspective on Scan Compression.	IEEE Design & Test of Computers	2008	DBLP DOI BibTeX RDF	scan compression, test data volume reduction, IC testing, test application time reduction
1	Subhasish Mitra	Tutorial 4: Robust System Design in Scaled CMOS.	ISQED	2008	DBLP DOI BibTeX RDF
1	Mridul Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, Kyunglok Kim, Bipul C. Paul, Wenping Wang, Bo Yang, Yu Cao, Subhasish Mitra	Optimized Circuit Failure Prediction for Aging: Practicality and Promise.	ITC	2008	DBLP DOI BibTeX RDF
1	Hiroaki Inoue, Yanjing Li, Subhasish Mitra	VAST: Virtualization-Assisted Concurrent Autonomous Self-Test.	ITC	2008	DBLP DOI BibTeX RDF
1	Sung-Boem Park, Subhasish Mitra	IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors.	DAC	2008	DBLP DOI BibTeX RDF	verification, debug, validation, design for debug
1	Tze Wee Chen, Kyunglok Kim, Young Moon Kim, Subhasish Mitra	Gate-Oxide Early Life Failure Prediction.	VTS	2008	DBLP DOI BibTeX RDF
1	Yanjing Li, Samy Makar, Subhasish Mitra	CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns.	DATE	2008	DBLP DOI BibTeX RDF
1	Neeraj Suri, Christof Fetzer, Jacob Abraham, Stefan Poledna, Avi Mendelson, Subhasish Mitra	Dependable Embedded Systems Special Day Panel: Issues and Challenges in Dependable Embedded Systems.	DATE	2008	DBLP DOI BibTeX RDF
1	Subhasish Mitra	Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges.	DATE	2008	DBLP DOI BibTeX RDF
1	Jie Zhang, Nishant Patil, Subhasish Mitra	Design Guidelines for Metallic-Carbon-Nanotube-Tolerant Digital Logic Circuits.	DATE	2008	DBLP DOI BibTeX RDF
1	Dimitris Gizopoulos, Kaushik Roy, Subhasish Mitra, Pia Sanda	Soft Errors: System Effects, Protection Techniques and Case Studies.	DATE	2008	DBLP DOI BibTeX RDF
1	Subhasish Mitra	Soft Error Protection Techniques.	IOLTS	2008	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Ravishankar K. Iyer, Kishor S. Trivedi, James W. Tschanz	Reliable system design: models, metrics and design techniques.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Igor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini	A low-overhead fault tolerance scheme for TSV-based 3D network on chip links.	ICCAD	2008	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-Dependent Delay Testing of FPGAs.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Mridul Agarwal	Circuit failure prediction to overcome scaled CMOS reliability challenges.	ITC	2007	DBLP DOI BibTeX RDF
1	Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey	California scan architecture for high quality and low power testing.	ITC	2007	DBLP DOI BibTeX RDF
1	Nishant Patil, Jie Deng, H.-S. Philip Wong, Subhasish Mitra	Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits.	DAC	2007	DBLP DOI BibTeX RDF
1	Mridul Agarwal, Bipul C. Paul, Ming Zhang, Subhasish Mitra	Circuit Failure Prediction and Its Application to Transistor Aging.	VTS	2007	DBLP DOI BibTeX RDF
1	Sanjit A. Seshia, Wenchao Li, Subhasish Mitra	Verification-guided soft error resilience.	DATE	2007	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Pia Sanda, Norbert Seifert	Soft Errors: Technology Trends, System Effects, and Protection Techniques.	IOLTS	2007	DBLP DOI BibTeX RDF	Memory soft errors, Logic soft errors, timing derating, logic derating, architectural derating, Built-In Soft Error Resilience, reliability, data integrity, availability, Error Correcting Codes, error detection, recovery, Soft errors, FITs, radiation hardening
1	Subhasish Mitra	Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.	IOLTS	2007	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Kee Sup Kim	XPAND: An Efficient Test Stimulus Compression Technique.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	XPAND, testing, compression, Built-In Self Test (BIST), compaction
1	Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Ming Zhang, Saad Waqas, Norbert Seifert, Balkaran S. Gill, Kee Sup Kim	Combinational Logic Soft Error Correction.	ITC	2006	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Test Compression for FPGAs.	ITC	2006	DBLP DOI BibTeX RDF
1	Nishant Patil, Subhasish Mitra, Steven S. Lumetta	Signature Analyzer Design for Yield Learning Support.	ITC	2006	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim	Soft Error Resilient System Design through Error Correction.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
1	Bob Mungamuru, Hector Garcia-Molina, Subhasish Mitra	How To Safeguard Your Sensitive Data.	SRDS	2006	DBLP DOI BibTeX RDF
1	Ruifeng Guo, Subhasish Mitra, Enamul Amyeen, Jinkyu Lee, Srihari Sivaraj, Srikanth Venkataraman	Evaluation of Test Metrics: Stuck-at, Bridge Coverage Estimate and Gate Exhaustive.	VTS	2006	DBLP DOI BibTeX RDF
1	T. M. Mak, Subhasish Mitra	Should Logic SER be Solved at the Circuit Level?	IOLTS	2006	DBLP DOI BibTeX RDF
1	Ravishankar K. Iyer, Nithin Nakka, Zbigniew Kalbarczyk, Subhasish Mitra	Recent Advances and New Avenues in Hardware-Level Reliability Support.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability, Error-checking, Testing and Fault-Tolerance, Redundant design
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Optimized reseeding by seed ordering and encoding.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Application-independent testing of FPGA interconnects.	IEEE Trans. on CAD of Integrated Circuits and Systems	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim	Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim.	IEEE Computer	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher, Nishant Patil	X-Tolerant Test Response Compaction.	IEEE Design & Test of Computers	2005	DBLP DOI BibTeX RDF	Testability, Built-In Test, VLSI Test
1	Zoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman	Enabling yield analysis with X-compact.	ITC	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim	Logic soft errors: a major barrier to robust platform design.	ITC	2005	DBLP DOI BibTeX RDF
1	Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey	Gate exhaustive testing.	ITC	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang	Logic soft errors in sub-65nm technologies design and CAD challenges.	DAC	2005	DBLP DOI BibTeX RDF	architectural vulnerability factor, built-in soft error resilience, derating, error blocking, error detection, recovery, soft error
1	Erik H. Volkerink, Subhasish Mitra	Response compaction with any number of unknowns using a new LFSR architecture.	DAC	2005	DBLP DOI BibTeX RDF	LFS, x-compact, compression, BIST, VLSI test
1	R. D. (Shawn) Blanton, Subhasish Mitra	Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. (PDF / PS)	VLSI Design	2005	DBLP DOI BibTeX RDF
1	T. M. Mak, Subhasish Mitra, Ming Zhang	DFT Assisted Built-In Soft Error Resilience.	IOLTS	2005	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Efficient Design Diversity Estimation for Combinational Circuits.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	common-mode failures, reliability, fault-tolerant computing, dependability, Error detection, design diversity
1	Subhasish Mitra, Kee Sup Kim	X-compact: an efficient response compaction technique.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Techniques and algorithms for fault grading of FPGA interconnect test configurations.	IEEE Trans. on CAD of Integrated Circuits and Systems	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey	Reconfigurable Architecture for Autonomous Self-Repair.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Vladimir Hahanov, Raimund Ubar, Subhasish Mitra	Conference Reports.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher	X-Tolerant Signature Analysis.	ITC	2004	DBLP DOI BibTeX RDF
1	Kenneth A. Brand, Erik H. Volkerink, Edward J. McCluskey, Subhasish Mitra	Speed Clustering of Integrated Circuits.	ITC	2004	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Interconnect Delay Testing of Designs on Programmable Logic Devices.	ITC	2004	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Defect and Fault Tolerance of Reconfigurable Molecular Computing.	FCCM	2004	DBLP DOI BibTeX RDF
1	Subhasish Mitra, Erik H. Volkerink, Edward J. McCluskey, Stefan Eichenberger	Delay Defect Screening using Process Monitor Structures.	VTS	2004	DBLP DOI BibTeX RDF
1	Edward J. McCluskey, Ahmad A. Al-Yamani, Chien-Mo James Li, Chao-Wen Tseng, Erik H. Volkerink, François-Fabien Ferhani, Edward Li, Subhasish Mitra	ELF-Murphy Data on Defects and Test Sets.	VTS	2004	DBLP DOI BibTeX RDF
1	Kee Sup Kim, Subhasish Mitra, Paul G. Ryan	Delay Defect Characteristics and Testing Strategies.	IEEE Design & Test of Computers	2003	DBLP DOI BibTeX RDF
1	David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish	H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing.	ITC	2003	DBLP DOI BibTeX RDF
1	Mehdi Baradaran Tahoori, Subhasish Mitra	Automatic Configuration Generation for FPGA Interconnect Testing.	VTS	2003	DBLP DOI BibTeX RDF
1	Erik H. Volkerink, Subhasish Mitra	Efficient Seed Utilization for Reseeding based Compression.	VTS	2003	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Bist Reseeding with very few Seeds.	VTS	2003	DBLP DOI BibTeX RDF

Publications of "Subhasish Mitra" ( http://dblp.L3S.de/Authors/Subhasish_Mitra )