Search results for "Sudeep Pasricha"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Nishit Ashok Kapadia, Sudeep Pasricha	A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands.	Integration	2012	DBLP DOI BibTeX RDF
1	Shirish Bahirat, Sudeep Pasricha	A Particle Swarm Optimization approach for synthesizing application-specific hybrid photonic networks-on-chip.	ISQED	2012	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	A Power Delivery Network Aware Framework for Synthesis of 3D Networks-on-Chip with Multiple Voltage Islands.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Sudeep Pasricha	A Framework for TSV Serialization-aware Synthesis of Application Specific 3D Networks-on-Chip.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	A Multi-Granularity Power Modeling Methodology for Embedded Processors.	IEEE Trans. VLSI Syst.	2011	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Yong Zou	A low overhead fault tolerant routing scheme for 3D Networks-on-Chip.	ISQED	2011	DBLP DOI BibTeX RDF
1	Soohyun Kwon, Sudeep Pasricha, Jeonghun Cho	POSEIDON: A framework for application-specific Network-on-Chip synthesis for heterogeneous chip multiprocessors.	ISQED	2011	DBLP DOI BibTeX RDF
1	Nishit Ashok Kapadia, Sudeep Pasricha	VISION: a framework for voltage island aware synthesis of interconnection networks-on-chip.	ACM Great Lakes Symposium on VLSI	2011	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Yong Zou	NS-FTR: A fault tolerant routing scheme for networks on chip with permanent and runtime intermittent faults.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Shirish Bahirat	OPAL: A multi-layer hybrid photonic NoC for 3D ICs.	ASP-DAC	2011	DBLP DOI BibTeX RDF
1	Jonathan Apodaca, Bobby Dalton Young, Luis Diego Briceno, Jay Smith, Sudeep Pasricha, Anthony A. Maciejewski, Howard Jay Siegel, Shirish Bahirat, Bhavesh Khemka, Adrian Ramirez, Yong Zou	Stochastically robust static resource allocation for energy minimization with a makespan constraint in a heterogeneous computing environment.	AICCSA	2011	DBLP DOI BibTeX RDF
1	Bobby Dalton Young, Jonathan Apodaca, Luis Diego Briceno, Jay Smith, Sudeep Pasricha, Anthony A. Maciejewski, Howard Jay Siegel, Bhavesh Khemka, Shirish Bahirat, Adrian Ramirez, Yong Zou	Energy-Constrained Dynamic Resource Allocation in a Heterogeneous Computing Environment.	ICPP Workshops	2011	DBLP DOI BibTeX RDF
1	Yong Zou, Yi Xiang, Sudeep Pasricha	Analysis of on-chip interconnection network interface reliability in multicore systems.	ICCD	2011	DBLP DOI BibTeX RDF
1	Brad K. Donohoo, Chris Ohlsen, Sudeep Pasricha	AURA: An application and user interaction aware middleware framework for energy optimization in mobile devices.	ICCD	2011	DBLP DOI BibTeX RDF
1	Yong Zou, Sudeep Pasricha	NARCO: Neighbor Aware Turn Model-Based Fault Tolerant Routing for NoCs.	Embedded Systems Letters	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Fadi J. Kurdahi, Nikil D. Dutt	Evaluating Carbon Nanotube Global Interconnects for Chip Multiprocessor Applications.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis.	IEEE Trans. VLSI Syst.	2010	DBLP DOI BibTeX RDF
1	Shirish Bahirat, Sudeep Pasricha	UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications.	ISQED	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Yong Zou, Dan Connors, Howard Jay Siegel	OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip.	CODES+ISSS	2010	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Nikil D. Dutt, Fadi J. Kurdahi	System-level PVT variation-aware power exploration of on-chip communication architectures.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	PVT variation, on-chip communication architectures, performance exploration, high-level synthesis, power estimation, digital systems
1	Gabor Madl, Sudeep Pasricha, Nikil Dutt, Sherif Abdelwahed	Cross-abstraction Functional Verification and Performance Analysis of Chip Multiprocessor Designs.	IEEE Trans. Industrial Informatics	2009	DBLP DOI BibTeX RDF
1	Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil D. Dutt, Minwook Ahn, Yunheung Paek	Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.	IEEE Trans. on CAD of Integrated Circuits and Systems	2009	DBLP DOI BibTeX RDF
1	Sudeep Pasricha	Exploring serial vertical interconnects for 3D ICs.	DAC	2009	DBLP DOI BibTeX RDF	serial interconnect, VLSI, networks on chip, 3D ICs
1	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi	Exploring Carbon Nanotube Bundle Global Interconnects for Chip Multiprocessor Applications.	VLSI Design	2009	DBLP DOI BibTeX RDF
1	Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha	A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.	MTV	2009	DBLP DOI BibTeX RDF
1	Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha	Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications.	ESTImedia	2009	DBLP DOI BibTeX RDF
1	Shirish Bahirat, Sudeep Pasricha	Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	photonic interconnect, network-on-chip, chip multiprocessor
1	Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based communication architectures at the CCATB abstraction.	ACM Trans. Embedded Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus
1	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency.	DAC	2008	DBLP DOI BibTeX RDF	dynamic resizing, performance, embedded processor, register file
1	Sudeep Pasricha, Nikil Dutt	ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.	ASP-DAC	2008	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt	Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Luis Angel D. Bathen, Nikil D. Dutt, Sudeep Pasricha	A framework for memory-aware multimedia application mapping on chip-multiprocessors.	ESTImedia	2008	DBLP DOI BibTeX RDF
1	Doosan Cho, Sudeep Pasricha, Ilya Issenin, Nikil Dutt, Yunheung Paek, SunJun Ko	Compiler driven data layout optimization for regular/irregular array access patterns.	LCTES	2008	DBLP DOI BibTeX RDF	compiler, memory hierarchy, energy consumption, data placement
1	Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum	Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors.	LCTES	2008	DBLP DOI BibTeX RDF	energy-delay, out-of-order embedded processor, resource resizing, performance, architecture
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	Methodology for multi-granularity embedded processor power model generation for an ESL design flow.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	system-on-chip, embedded processor, power modeling, esl
1	Chulho Shin, Peter Grun, Nizar Romdhane, Christopher K. Lennard, Gabor Madl, Sudeep Pasricha, Nikil Dutt, Mark Noll	Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications.	Design Autom. for Emb. Sys.	2007	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt	A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.	IEEE Trans. on CAD of Integrated Circuits and Systems	2007	DBLP DOI BibTeX RDF
1	Nikil Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
1	Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi, Nikil Dutt	System level power estimation methodology with H.264 decoder prediction IP case study.	ICCD	2007	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	FABSYN: floorplan-aware bus architecture synthesis.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Gabor Madl, Sudeep Pasricha, Luis Angel D. Bathen, Nikil Dutt, Qiang Zhu	Formal performance evaluation of AMBA-based system-on-chip designs.	EMSOFT	2006	DBLP DOI BibTeX RDF	performance evaluation, model checking, system-on-chip
1	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Constraint-driven bus matrix synthesis for MPSoC.	ASP-DAC	2006	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt	COSMECA: application specific co-synthesis of memory and communication architectures for MPSoC.	DATE	2006	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
1	Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane	Floorplan-aware automated synthesis of bus-based communication architectures.	DAC	2005	DBLP DOI BibTeX RDF	systems-on-chip, communication synthesis
1	Sudeep Pasricha, Mohamed Ben-Romdhane	Using TLM for Exploring Bus-based SoC Communication Architectures.	ASAP	2005	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil Dutt, Mohamed Ben-Romdhane	Automated throughput-driven synthesis of bus-based communication architectures.	ASP-DAC	2005	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Manev Luthra, Shivajit Mohapatra, Nikil D. Dutt, Nalini Venkatasubramanian	Dynamic Backlight Adaptation for Low-Power Handheld Devices.	IEEE Design & Test of Computers	2004	DBLP DOI BibTeX RDF
1	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Extending the transaction level modeling approach for fast communication architecture exploration.	DAC	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
1	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
1	Sudeep Pasricha, Shivajit Mohapatra, Manev Luthra, Nikil D. Dutt, Nalini Venkatasubramanian	Reducing Backlight Power Consumption for Streaming Video Applications on Mobile Handheld Devices.	ESTImedia	2003	DBLP BibTeX RDF
1	Sudeep Pasricha, Alexander V. Veidenbaum	Improving Branch Prediction Accuracy in Embedded Processors in the Presence of Context Switches.	ICCD	2003	DBLP DOI BibTeX RDF

Publications of "Sudeep Pasricha" ( http://dblp.L3S.de/Authors/Sudeep_Pasricha )