| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Saumya Chandra, Anand Raghunathan, Sujit Dey |
Variation-Aware Voltage Level Selection.  |
IEEE Trans. VLSI Syst.  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Vivek J. Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey |
VESPA: Variability emulation for System-on-Chip performance analysis. |
DATE |
2011 |
DBLP BibTeX RDF |
|
| 1 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Variation-Aware System-Level Power Analysis. |
IEEE Trans. VLSI Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaoxuan Wang, Sujit Dey |
Addressing Response Time and Video Quality in Remote Server Based Internet Mobile Gaming. |
WCNC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaoxuan Wang, Sujit Dey |
Rendering Adaptation to Address Communication and Computation Constraints in Cloud Mobile Gaming. |
GLOBECOM |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shoubhik Mukhopadhyay, Curt Schurgers, Sujit Dey |
Enabling rich mobile applications: joint computation and communication scheduling. |
Mobile Computing and Communications Review |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shoubhik Mukhopadhyay, Curt Schurgers, Debashis Panigrahi, Sujit Dey |
Model-Based Techniques for Data Reliability in Wireless Sensor Networks. |
IEEE Trans. Mob. Comput. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Variation-Tolerant Dynamic Power Management at the System-Level. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaoxuan Wang, Sujit Dey |
Modeling and Characterizing User Experience in a Cloud Server Based Mobile Gaming Approach. |
GLOBECOM |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nilanjan Banerjee, Saumya Chandra, Swaroop Ghosh, Sujit Dey, Anand Raghunathan, Kaushik Roy |
Coping with Variations through System-Level Design. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Yi Zhao, Sujit Dey |
Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Xiaoliang Bai, Sujit Dey |
Evaluating Transient Error Effects in Digital Nanometer Circuits. |
IEEE Transactions on Reliability |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Naomi Ramos, Debashis Panigrahi, Sujit Dey |
Dynamic adaptation policies to improve quality of service of real-time multimedia applications in IEEE 802.11e WLAN Networks. |
Wireless Networks |
2007 |
DBLP DOI BibTeX RDF |
Quality of service, Wireless LAN, Service level agreements, Video streaming, IEEE 802.11e |
| 1 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
System-on-Chip Power Management Considering Leakage Power Variations. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Shoubhik Mukhopadhyay, Curt Schurgers, Sujit Dey |
Joint Computation and Communication Scheduling to Enable Rich Mobile Applications. |
GLOBECOM |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Sujit Dey |
Modeling soft error effects considering process variations. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Sujit Dey |
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO). |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Sujit Dey |
Evaluating and Improving Transient Error Tolerance of CMOS Digital VLSI Circuits. |
ITC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Considering process variations during system-level power analysis. |
ISLPED |
2006 |
DBLP DOI BibTeX RDF |
system-on-chip, low power design, process variations, power analysis, power estimation |
| 1 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Naomi Ramos, Debashis Panigrahi, Sujit Dey |
Quality of service provisioning in 802.11e networks: challenges, approaches, and future directions. |
IEEE Network |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Sujit Dey, Xiaoliang Bai |
Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. |
IEEE Design & Test of Computers |
2005 |
DBLP DOI BibTeX RDF |
B.8.1 Reliability, G.4.g Reliability and robustness, B.7 Integrated Circuits, Testing and Fault-Tolerance |
| 1 | Chong Zhao, Xiaoliang Bai, Sujit Dey |
A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Yi Zhao, Sujit Dey |
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
circuit hardening, nanometer circuits, robustness calibration, robustness insertion |
| 1 | Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
communication architectures, on-chip bus |
| 1 | Saumya Chandra, Sujit Dey |
Addressing Computational and Networking Constraints to Enable Video Streaming from Wireless Appliances. |
ESTImedia |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Jennifer L. Wong, Miodrag Potkonjak, Sujit Dey |
Optimizing designs using the addition of deflection operations. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey |
Common-case computation: a high-level energy and performance optimization technique. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
Design of high-performance system-on-chips using communication architecture tuners. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Weidong Wang, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
Resource budgeting for Multiprocess High-level synthesis. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas |
Interconnect coupling-aware driver modeling in static noise analysis for nanometer circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoliang Bai, Sujit Dey |
High-level crosstalk defect Simulation methodology for system-on-chip interconnects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Efficient power profiling for battery-driven embedded system design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Design space exploration for optimizing on-chip communication architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Zhao, Sujit Dey, Li Chen |
Double sampling data checking technique: an online testing solution for multisource noise-induced errors on on-chip interconnects and buses. |
IEEE Trans. VLSI Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Chong Zhao, Xiaoliang Bai, Sujit Dey |
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
compound noise effect, nano-meter technology, softness distribution, robustness |
| 1 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Debashis Panigrahi, Sujit Dey |
CHASER: content and channel aware object scheduling and error control for wireless Web access in 3G networks. |
PIMRC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong-Gi Lee, Sujit Dey |
Dynamic image adaptation technique and architecture to enhance server performance in wireless image services. |
PIMRC |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Zhao, Sujit Dey |
Fault-coverage analysis techniques of crosstalk in chip interconnects. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
High-level macro-modeling and estimation techniques for switching activity and power consumption. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Krishna Sekar, Sujit Dey |
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. |
J. Electronic Testing |
2003 |
DBLP DOI BibTeX RDF |
LI-BIST, crosstalk test, BIST, SoC test, low-power test |
| 1 | Xiaoliang Bai, Rajit Chandra, Sujit Dey, P. V. Srinivas |
Noise-Aware Driver Modeling for Nanometer Technology. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoliang Bai, Sujit Dey, Angela Krstic |
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit Dey |
A scalable software-based self-test methodology for programmable processors. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
scalability, microprocessor, at-speed test, software-based self-test, test program, manufacturing test |
| 1 | Weidong Wang, Niraj K. Jha, Anand Raghunathan, Sujit Dey |
High-level Synthesis of Multi-process Behavioral Descriptions. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Zhao, Sujit Dey |
Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. |
IOLTS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Dong-Gi Lee, Sujit Dey |
Addressing Server Latency and Capacity to Enable Fast and Affordable Wireless Image Data Services. |
ESTImedia |
2003 |
DBLP BibTeX RDF |
|
| 1 | Krishna Sekar, Kanishka Lahiri, Sujit Dey |
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
ASIC |
| 1 | Faraydon Karim, Anh Nguyen, Sujit Dey |
An Interconnect Architecture for Networking Systems on Chips. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Cosimulation-based power estimation for system-on-chip design. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Xiaoliang Bai, Sujit Dey |
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. |
J. Electronic Testing |
2002 |
DBLP DOI BibTeX RDF |
interconnect, crosstalk, processor, self-test |
| 1 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded Software-Based Self-Test for Programmable Core-Based Designs. |
IEEE Design & Test of Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
Communication-Based Power Management. |
IEEE Design & Test of Computers |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Clark N. Taylor, Debashis Panigrahi, Sujit Dey |
Design of an Adaptive Architecture for Energy Efficient Wireless Image Communication. |
Embedded Processor Design Challenges |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Zhao, Li Chen, Sujit Dey |
On-Line Testing of Multi-Source Noise-Induced Errors on the Interconnects and Buses of System-on-Chips. |
ITC |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Sujit Dey |
Software-based diagnosis for processors. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
microprocessor, self-test, instruction, diagnostics |
| 1 | Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li Chen, Sujit Dey |
Embedded software-based self-testing for SoC design. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
functional test, SoC test, VLSI test, microprocessor test |
| 1 | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
Communication architecture based power management for battery efficient system design. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
battery efficiency, embedded systems, low power design, power management, communication architectures |
| 1 | Krishna Sekar, Sujit Dey |
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | C.-H. Chia, Sujit Dey, Faraydon Karim, Haluk Konuk, Keesup Kim |
Validation and Test of Network Processors and ASICs. (PDF / PS) |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi |
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Luciano Lavagno, Sujit Dey, Rajesh K. Gupta |
Specification, Modeling and Design Tools for System-on-Chip (Tutorial Abstract). |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Debashis Panigrahi, Clark N. Taylor, Sujit Dey |
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. |
VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Adaptive, image compression, reconfigurable architecture, wireless multimedia |
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Fast system-level power profiling for battery-efficient system design. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Sujit Dey |
Software-based self-testing methodology for processor cores. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
System-level performance analysis for designing on-chipcommunication architectures. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Clark N. Taylor, Sujit Dey, Yi Zhao |
Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Xiaoliang Bai, Sujit Dey |
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Faraydon Karim, Anh Nguyen, Sujit Dey, Ramesh R. Rao |
On-Chip Communication Architecture for OC-768 Network Processors. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoliang Bai, Sujit Dey |
High-level Crosstalk Defect Simulation for System-on-Chip Interconnects. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
System-on-Chip, Crosstalk, Interconnect test, Defect simulation, High level |
| 1 | Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan |
Battery Life Estimation of Mobile Embedded Systems. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand Raghunathan, Sujit Dey |
Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. |
VLSI Design |
2001 |
DBLP BibTeX RDF |
|
| 1 | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Indradeep Ghosh, Sujit Dey, Niraj K. Jha |
A fast and low-cost testing technique for core-based system-chips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Sujit Dey, Debashis Panigrahi, Li Chen, Clark N. Taylor, Krishna Sekar, Pablo Sanchez |
Using a Soft Core in a SoC Design: Experiences with picoJava. |
IEEE Design & Test of Computers |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi Zhao, Sujit Dey |
Analysis of interconnect crosstalk defect coverage of test sets. |
ITC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar, Ying Cheng |
Embedded hardware and software self-testing methodologies for processor cores. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwang-Ting Cheng, Sujit Dey, Mike Rodgers, Kaushik Roy |
Test challenges for deep sub-micron technologies. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey |
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoliang Bai, Sujit Dey, Janusz Rajski |
Self-test methodology for at-speed test of crosstalk in chip interconnects. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Li Chen, Sujit Dey |
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
microprocessor, self-test, instructions, structural testing, At-speed testing |
| 1 | Kanishka Lahiri, Sujit Dey, Anand Raghunathan |
Performance Analysis of Systems with Multi-Channel Communication Architectures. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno |
Efficient Power Co-Estimation Techniques for System-on-Chip Design. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Efficient Exploration of the SoC Communication Architecture Design Space. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Yervant Zorian, Sujit Dey, Mike Rodgers |
Test of Future System-on-Chips. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Sujit Dey, Anand Raghunathan, Niraj K. Jha, Kazutoshi Wakabayashi |
Controller-based power management for control-flow intensive designs. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Indradeep Ghosh, Niraj K. Jha, Sujit Dey |
A low overhead design for testability and test generation technique for core-based systems-on-a-chip. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Srimat T. Chakradhar, Sujit Dey |
Resynthesis and retiming for optimum partial scan. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Yervant Zorian, Erik Jan Marinissen, Sujit Dey |
Testing Embedded-Core-Based System Chips. |
IEEE Computer |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey |
Power management in high-level synthesis. |
IEEE Trans. VLSI Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey |
Common-Case Computation: A High-Level Technique for Power and Performance Optimization. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Roy, Anand Raghunathan, Sujit Dey |
Low Power Design Methodologies for Systems-on-Chips. |
VLSI Design |
1999 |
DBLP BibTeX RDF |
|
| 1 | Kanishka Lahiri, Anand Raghunathan, Sujit Dey |
Fast performance analysis of bus-based system-on-chip communication architectures. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Michael Cuviello, Sujit Dey, Xiaoliang Bai, Yi Zhao |
Fault modeling and simulation for crosstalk in system-on-chip interconnects. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Subhrajit Bhattacharya, Sujit Dey, Franc Brglez |
Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization. |
ACM Trans. Design Autom. Electr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
resorce sharing, high-level synthesis, clock period |
| 1 | Sujit Dey, Vijay Gangaram, Miodrag Potkonjak |
A controller redesign technique to enhance testability of controller-data path circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Srivaths Ravi, Indradeep Ghosh, Rabindra K. Roy, Sujit Dey |
Controller Resynthesis for Testability Enhancement of RTL Controller/Data Path Circuits. |
J. Electronic Testing |
1998 |
DBLP DOI BibTeX RDF |
controller resynthesis, test synthesis, high-level testing |
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