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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 5 occurrences of 4 keywords
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Results
Found 15 publication records. Showing 15 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla |
High Level Power Estimation Models for FPGAs.  |
ISVLSI  |
2011 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla |
Power Aware High Level Synthesis of Hardware Coprocessors.  |
J. Low Power Electronics  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla |
Coprocessor design space exploration using high level synthesis.  |
ISQED  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Jens Brandt, Klaus Schneider, Sumit Ahuja, Sandeep K. Shukla |
The Model Checking View to Clock Gating and Operand Isolation.  |
ACSD  |
2010 |
DBLP DOI BibTeX RDF |
operand isolation, model checking, clock gating |
| 1 | Sumit Ahuja, Wei Zhang, Sandeep K. Shukla |
System level simulation guided approach to improve the efficacy of clock-gating.  |
HLDVT  |
2010 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Wei Zhang, Avinash Lakshminarayana, Sandeep K. Shukla |
A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms.  |
VLSI Design  |
2010 |
DBLP DOI BibTeX RDF |
C2R, Hardware Coprocessor, Software Algorithms, High Level Synthesis, Clock-gating, Power Reduction |
| 1 | Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla |
SCoPE: Statistical Regression Based Power Models for Co-Processors Power Estimation.  |
J. Low Power Electronics  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Swathi T. Gurumani, Chad Spackman, Sandeep K. Shukla |
Hardware Coprocessor Synthesis from an ANSI C Specification.  |
IEEE Design & Test of Computers  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar |
Power estimation methodology for a high-level synthesis framework.  |
ISQED  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Deepak Mathaikutty, Avinash Lakshminarayana, Sandeep K. Shukla |
Accurate power estimation of hardware co-processors using system level simulation.  |
SoCC  |
2009 |
DBLP DOI BibTeX RDF |
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| 1 | Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla |
Applying Verification Collaterals for Accurate Power Estimation.  |
MTV  |
2008 |
DBLP DOI BibTeX RDF |
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| 1 | Gaurav Singh, Jacob B. Schwartz, Sumit Ahuja, Sandeep K. Shukla |
Techniques for Power-Aware Hardware Synthesis from Concurrent Action Oriented Specifications.  |
J. Low Power Electronics  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Eric Simpson, Pengyuan Yu, Patrick Schaumont, Sumit Ahuja, Sandeep K. Shukla |
VT Matrix Multiply Design for MEMOCODE '07.  |
MEMOCODE  |
2007 |
DBLP DOI BibTeX RDF |
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| 1 | Gaurav Singh, S. S. Ravi, Sumit Ahuja, Sandeep K. Shukla |
Complexity of Scheduling in Synthesizing Hardware from Concurrent Action Oriented Specifications.  |
Power-aware Computing Systems  |
2007 |
DBLP BibTeX RDF |
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| 1 | Sumit Ahuja, Deepak Mathaikutty, Sandeep K. Shukla, Ajit Dingankar |
Assertion-Based Modal Power Estimation.  |
MTV  |
2007 |
DBLP DOI BibTeX RDF |
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Displaying result #1 - #15 of 15 (100 per page; Change: )
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