| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Sangho Shin, Kyungmin Kim, Sung-Mo Kang |
Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs.  |
Proceedings of the IEEE  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang |
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. |
J. Low Power Electronics |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyosun Kim, Sangho Shin, Sung-Mo Kang |
Field Programmable Stateful Logic Array. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kyosun Kim, Sung-Mo Kang |
Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Kyosun Kim, Sangho Shin, Sung-Mo Kang |
Stateful logic pipeline architecture. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kyungmin Kim, Sung-Mo Kang |
Complementary structure of memristive devices based passive memory arrays. |
ISCAS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kyungmin Kim, Sung-Mo Kang |
Compact Models for Memristors Based on Charge-Flux Constitutive Relationships. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kyungmin Kim, Sung-Mo Kang |
Data-Dependent Statistical Memory Model for Passive Array of Memristive Devices. |
IEEE Trans. on Circuits and Systems |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang |
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang |
Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Jae-Jin Jung, Kwang-Hyun Baek, Shin-Il Lim, Suki Kim, Sung-Mo Kang |
Design of a 6 bit 1.25 GS/s DAC for WPAN. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Sin Kim, Sung-Mo Kang |
A 8-Gb/s/pin current mode multi-level simultaneous bidirectional I/O. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Seokoh Yun, Sanghyun Cho, Jongmoon Kim, Minseok Kang, Wonkab Oh, Sung-Mo Kang |
0.18um CMOS integrated chipset for 5.8GHz DSRC systems with +10dBm output power. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Sin Kim, Sung-Mo Kang |
Programmable High Speed Multi-Level Simultaneous Bidirectional I/O. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu |
Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Yong Sin Kim, Sangho Shin, Sung-Mo Kang |
A 4-Gb/s/pin current mode 4-level simultaneous bidirectional I/O with current mismatch calibration. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kwyro Lee, Sung-Mo Kang |
Low-power 2.4GHz CMOS frequency synthesizer with differentially controlled MOS varactors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Sangho Shin, Kwyro Lee, Sung-Mo Kang |
2.4GHz ZigBee radio architecture with fast frequency offset cancellation loop. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A 32-bit carry lookahead adder using dual-path all-N logic. |
IEEE Trans. VLSI Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Yong Sin Kim, Sung-Mo Kang |
Current mode multi-level simultaneous bidirectional I/O scheme for chip-to-chip communications. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Zhongda Wang, Sung-Mo Kang |
Low Power and High Performance Circuit Techniques for High Fan-In Dynamic Gates. |
ISQED |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Zhongda Wang, Sung-Mo Kang |
Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
| 1 | Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang |
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. |
ISCAS |
2004 |
DBLP BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Sung-Mo Kang |
Minimum delay optimization for domino circuits - a coupling-aware approach. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
Logic synthesis, coupling, domino logic, delay minimization |
| 1 | Jaesik Lee, Ki-Wook Kim, Yoonjong Huh, Peter Bendix, Sung-Mo Kang |
Chip-level charged-device modeling and simulation in CMOS integrated circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Timing constraints for domino logic gates with timing-dependent keepers. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang |
Energy-efficient skewed static logic with dual Vt: design and synthesis. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware interconnect power optimization in domino logic synthesis. |
IEEE Trans. VLSI Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang |
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters. |
ISVLSI |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Sung-Mo Kang |
Elements of low power design for integrated systems. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
low power integrated circuits, VLSI, CMOS |
| 1 | Yong Sin Kim, Soo Hwan Kim, Kwang-Hyun Baek, Suki Kim, Sung-Mo Kang |
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers. |
VLSI Design |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwang-Hyun Baek, Myung-Jun Choe, Edward Merlo, Sung-Mo Kang |
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs. |
ISCAS |
2003 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu |
Logic transformation for low-power synthesis. |
ACM Trans. Design Autom. Electr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
logic transformation, power estimation model, low power, Logic synthesis |
| 1 | Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang |
Domino logic synthesis based on implication graph. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained transistor sizing and power optimization for dual Vst domino logic. |
IEEE Trans. VLSI Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. |
ISVLSI |
2002 |
DBLP DOI BibTeX RDF |
keeper, optimal timing, noise, skew, domino logic, dynamic circuit |
| 1 | Robert K. Grube, Qi Wang, Sung-Mo Kang |
Design limitations in deep sub-0.1µm CMOS SRAM. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
GIDL, on-chip cache, tunneling currents, gate leakage |
| 1 | Sung-Mo Kang |
On-chip thermal engineering for peta-scale integration. |
ISPD |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaesik Lee, Ki-Wook Kim, Sung-Mo Kang |
VeriCDF: a new verification methodology for charged device failures. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
simulation, modeling, reliability |
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Low-swing clock domino logic incorporating dual supply and dual threshold voltages. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
low swing clock, low power, domino logic, dual supply voltage, dual threshold voltage |
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. |
DATE |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Kwang-Hyun Baek, Myung-Jun Choe, Sung-Mo Kang |
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance. |
ISCAS |
2002 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Sung-Mo Kang |
Crosstalk noise minimization in domino logic design. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Ahn, Seung-Moon Yoo, Sung-Mo Kang |
Effective algorithms for cache-level compression. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaushik Roy, Sung-Mo Kang, Cheng-Kok Koh (eds.) |
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, West Lafayette, Indiana, USA, 2001 |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang |
2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Transistor sizing for reliable domino logic design in dual threshold voltage technologies. |
ACM Great Lakes Symposium on VLSI |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang |
Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. |
DAC |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang |
New current-mode sense amplifiers for high density DRAM and PIM architectures. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang |
Energy-efficient skewed static logic design with dual Vt. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang |
Skew-tolerant high-speed (STHS) domino logic. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Chulwoo Kim, Sung-Mo Kang |
A low-power reduced swing single clock flip-flop. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinghong Chen, Sung-Mo Kang |
Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang |
Coupling-aware minimum delay optimization for domino logic circuits. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang |
Full chip ESD design rule checking. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang |
ESD design rule checker. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang |
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Q. Li, Sung-Mo Kang |
Trapezoid-to-simple polygon recomposition for resistance extraction. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang |
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang |
Noise constrained power optimization for dual VT domino logic. |
ISCAS |
2001 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang |
Understanding and Addressing the Noise Induced By Electrostatic Discharge in Multiple Power Supply Systems. |
ICCD |
2001 |
DBLP BibTeX RDF |
|
| 1 | Ching-Han Tsai, Sung-Mo Kang |
Cell-level placement for improving substrate thermal distribution. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Kan Cheng, Sung-Mo Kang |
A temperature-aware simulation environment for reliable ULSI chipdesign. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang |
Interconnect thermal modeling for accurate simulation of circuittiming and reliability. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang |
Noise-aware power optimization for on-chip interconnect. |
ISLPED |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Qiao Li, Sung-Mo Kang |
Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
edge pair, non-Manhattan layout extraction, polygon to trapezoid decomposition, scanline algorithm, scanline interval |
| 1 | Qiao Li, Sung-Mo Kang |
Technology independent arbitrary device extractor. |
ACM Great Lakes Symposium on VLSI |
2000 |
DBLP DOI BibTeX RDF |
arbitrary device extraction, device model specification, technology independent layout extraction |
| 1 | Ching-Han Tsai, Sung-Mo Kang |
Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Unni Narayanan, Sung-Mo Kang |
Domino logic synthesis minimizing crosstalk. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | N. S. Nagaraj, Andrzej J. Strojwas, Sani R. Nassif, Ray Hokinson, Tak Young, Wonjae L. Kang, David Overhauser, Sung-Mo Kang |
When bad things happen to good chips (panel session). |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Jay R. Moorman, John W. Lockwood, Sung-Mo Kang |
Real-time prioritized call admission control in a base station scheduler. |
WOWMOM |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang |
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. |
ICCAD |
2000 |
DBLP BibTeX RDF |
|
| 1 | Chulwoo Kim, Jaesik Lee, Kwang-Hyun Baek, Eric Martina, Sung-Mo Kang |
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology. (PDF / PS) |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Sung-Mo Kang |
No-Race Charge-Recycling Differential Logic (NCDL). |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Chulwoo Kim, Seung-Moon Yoo, Sung-Mo Kang |
NMOS Energy Recovery Logic. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang |
Interconnect thermal modeling for determining design limits on current density. |
ISPD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Han Tsai, Sung-Mo Kang |
Standard cell placement for even on-chip thermal distribution. |
ISPD |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang |
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. |
DAC |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu |
Logic Transformation for Low Power Synthesis. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Seung-Moon Yoo, Sung-Mo Kang |
CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Jinghong Chen, Sung-Mo Kang |
A mixed frequency-time approach for quasi-periodic steady-state simulation of multi-level modeled circuits. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Kan Cheng, Sung-Mo Kang |
Temperature-driven power and timing analysis for CMOS ULSI circuits. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Ching-Han Tsai, Sung-Mo Kang |
Macrocell placement with temperature profile optimization. |
ISCAS |
1999 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Kan Cheng, Sung-Mo Kang |
An efficient method for hot-spot identification in ULSI circuits. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Ki-Wook Kim, C. L. Liu, Sung-Mo Kang |
Implication graph based domino logic synthesis. |
ICCAD |
1999 |
DBLP BibTeX RDF |
|
| 1 | Haoran Duan, John W. Lockwood, Sung-Mo Kang |
Matrix unit cell scheduler (MUCS) for input-buffered ATM switches. |
IEEE Communications Letters |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang |
ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang |
Statistical estimation of average power dissipation using nonparametric techniques. |
IEEE Trans. VLSI Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Tong Li, Sung-Mo Kang |
Layout Extraction and Verification Methodology CMOS I/O Circuits. |
DAC |
1998 |
DBLP DOI BibTeX RDF |
congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins |
| 1 | Tong Li, Ching-Han Tsai, Sung-Mo Kang |
Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress. |
ICCAD |
1998 |
DBLP DOI BibTeX RDF |
|
| 1 | Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang |
iTEM: a temperature-dependent electromigration reliability diagnosis tool. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Brent K. Whitlock, Petar K. Pepeljugoski, Daniel M. Kuchta, John D. Crow, Sung-Mo Kang |
Computer Modeling and Simulation of the Optoelectronic Technology Consortium (OETC) Optical Bus. |
IEEE Journal on Selected Areas in Communications |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-Pen Yuan, Sung-Mo Kang |
A sequential procedure for average power analysis of sequential circuits. |
ISLPED |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Kim, Sung-Mo Kang |
An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Li-Pen Yuan, Chin-Chi Teng, Sung-Mo Kang |
Statistical Estimation of Average Power Dissipation in Sequential Circuits. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
| 1 | Sueng-Yong Park, Vaduvur Bharghavan, Sung-Mo Kang |
Data Link Level Support for Handoff in Wireless ATM Network. |
ICC |
1997 |
DBLP BibTeX RDF |
|
| 1 | Haoran Duan, John W. Lockwood, Sung-Mo Kang, J. D. Will |
A High-Performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches. |
INFOCOM |
1997 |
DBLP BibTeX RDF |
|
| 1 | Ashfaq Hossain, Sung-Mo Kang, Bob Horst |
Performance Comparison of Video Transport over ATM and ServerNet Interconnects. |
ICMCS |
1997 |
DBLP BibTeX RDF |
|
| 1 | Anthony M. Hill, Sung-Mo Kang |
Determining accuracy bounds for simulation-based switching activity estimation. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaewon Kim, Sung-Mo Kang |
A new triple-layer OTC channel router. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
1996 |
DBLP DOI BibTeX RDF |
|
![[Valid RSS]](Pics/valid-rss.png "Validate my RSS feed")