| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Bhavitavya Bhadviya, Ayan Mandal, Sunil P. Khatri |
Alleviating NBTI-induced failure in off-chip output drivers.  |
ACM Great Lakes Symposium on VLSI  |
2012 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra |
A fast, source-synchronous ring-based network-on-chip design. |
DATE |
2012 |
DBLP BibTeX RDF |
|
| 1 | Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth |
Noise-based Deterministic Logic and Computing: a Brief Survey. |
IJUC |
2011 |
DBLP BibTeX RDF |
|
| 1 | Pey-Chang Kent Lin, Ayan Mandal, Sunil P. Khatri |
Boolean Satisfiability using Noise Based Logic |
CoRR |
2011 |
DBLP BibTeX RDF |
|
| 1 | Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth |
Noise-based information processing: Noise-based logic and computing: what do we have so far? |
CoRR |
2011 |
DBLP BibTeX RDF |
|
| 1 | Didem Zeliha Turker, Sunil P. Khatri, Edgar Sánchez-Sinencio |
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. |
IEEE Trans. on Circuits and Systems |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra |
An Automated Approach for Minimum Jitter Buffered H-Tree Construction. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra |
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. |
VLSI Design |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Pey-Chang Kent Lin, Alex Ivanov, Bradley Johnson, Sunil P. Khatri |
A novel cryptographic key exchange scheme using resistors. |
ICCD |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Jayakumar, Sunil P. Khatri |
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. |
ACM Trans. Design Autom. Electr. Syst. |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Laszlo B. Kish, Sunil P. Khatri, Tamás Horváth |
Computation using Noise-based Logic: Efficient String Verification over a Slow Communication Channel |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Laszlo B. Kish, Sunil P. Khatri, Sergey M. Bezrukov, Ferdinand Peper, Zoltan Gingl, Tamás Horváth |
Noise-based deterministic logic and computing: a brief survey |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Laszlo B. Kish, Sunil P. Khatri, Ferdinand Peper |
Instantaneous noise-based logic |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Zoltan Gingl, Sunil P. Khatri, Laszlo B. Kish |
Towards brain-inspired computing |
CoRR |
2010 |
DBLP BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Fault Table Computation on GPUs. |
J. Electronic Testing |
2010 |
DBLP BibTeX RDF |
|
| 1 | Pey-Chang Kent Lin, Sunil P. Khatri |
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
NLFSR, stream cipher, pseudo-random sequence |
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Boolean satisfiability on a graphics processor. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
survey propagation, gpgpu, boolean satisfiability |
| 1 | Kalyana C. Bollapalli, Sunil P. Khatri, Laszlo B. Kish |
Implementing digital logic with sinusoidal supplies. |
DATE |
2010 |
DBLP BibTeX RDF |
|
| 1 | Rajesh Kumar, Sunil P. Khatri |
An efficient pulse flip-flop based launch-on-shift scan cell. |
ISCAS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Navid Abedini, Sunil P. Khatri, Serap A. Savari |
A SAT-Based Scheme to Determine Optimal Fix-Free Codes. |
DCC |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Karkala, Joseph Wanstrath, Travis Lacour, Sunil P. Khatri |
Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. |
ICCAD |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan |
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
Selective Forward Body Bias for High Speed and Low Power SRAMs. |
J. Low Power Electronics |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Suganth Paul, Sunil P. Khatri, Srinivas Patil, Abhijit Jas |
FPGA-based hardware acceleration for Boolean satisfiability. |
ACM Trans. Design Autom. Electr. Syst. |
2009 |
DBLP DOI BibTeX RDF |
Boolean satisfiabilty (SAT), boolean constant propagation (BCP), conflict induced clauses, non-chronological backtrack, FPGA |
| 1 | Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri |
Efficient On-Chip Crosstalk Avoidance CODEC Design. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri |
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi |
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. |
IEEE Trans. VLSI Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajballav Dash, Rajesh Garg, Sunil P. Khatri, Gwan S. Choi |
SEU hardened clock regeneration circuits. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Suganth Paul, Rajesh Garg, Sunil P. Khatri, Sheila Vaidya |
Design and implementation of a sub-threshold BFSK transmitter. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Fault table generation using Graphics Processing Units. |
HLDVT |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
Low power and high performance sram design using bank-based selective forward body bias. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
low power, high performance, body bias |
| 1 | Jeff L. Cobb, Kanupriya Gulati, Sunil P. Khatri |
Robust window-based multi-node technology-independent logic minimization. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
binary decision diagrams, boolean relation |
| 1 | Rajesh Garg, Sunil P. Khatri |
Efficient analytical determination of the SEU-induced pulse shape. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Accelerating statistical static timing analysis using graphics processing units. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry |
Fast circuit simulation on graphics processing units. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri, Peng Li |
Closed-loop modeling of power and temperature profiles of FPGAs. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
sub-threshold leakage, dynamic power |
| 1 | Srikanth Alaparthi, Kanupriya Gulati, Sunil P. Khatri |
Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. |
ISCAS |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Kumar, Vinay Karkala, Rajesh Garg, Tanuj Jindal, Sunil P. Khatri |
A radiation tolerant Phase Locked Loop design for digital electronics. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Kalyana C. Bollapalli, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri |
On-chip bidirectional wiring for heavily pipelined systems using network coding. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Sunil P. Khatri |
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Kumar, Kalyana C. Bollapalli, Rajesh Garg, Tarun Soni, Sunil P. Khatri |
A robust pulsed flip-flop and its use in enhanced scan design. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Vinay Karkala, Kalyana C. Bollapalli, Rajesh Garg, Sunil P. Khatri |
A PLL design based on a standing wave resonant oscillator. |
ICCD |
2009 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri |
SAT-based ATPG using multilevel compatible don't-cares. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Boolean satisfiabilty (SAT), testing, Automatic test pattern generation (ATPG), don't cares |
| 1 | Sabyasachi Das, Sunil P. Khatri |
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Mandar Waghmode, Sunil P. Khatri, Weiping Shi |
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. |
IET Computers & Digital Techniques |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | A. Kapoor, Nikhil Jayakumar, Sunil P. Khatri |
Dynamically De-Skewable Clock Distribution Methodology. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sabyasachi Das, Sunil P. Khatri |
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. |
IEEE Trans. VLSI Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sabyasachi Das, Sunil P. Khatri |
A Timing-Driven Approach to Synthesize Fast Barrel Shifters. |
IEEE Trans. on Circuits and Systems |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri, D. M. H. Walker |
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. |
Integration |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Improving FPGA routability using network coding. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
FPGA, network coding |
| 1 | Arunprasad Venkatraman, Rajesh Garg, Sunil P. Khatri |
A robust, fast pulsed flip-flop design. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
flip-flop, latch |
| 1 | Salman Gopalani, Rajesh Garg, Sunil P. Khatri, Mosong Cheng |
A lithography-friendly structured ASIC design approach. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
ASIC, OPC, lithography |
| 1 | Suganth Paul, Rajesh Garg, Sunil P. Khatri |
Pipelined network of PLA based circuit design. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
synchronous, pipelining, PLA |
| 1 | Kanupriya Gulati, Sunil P. Khatri |
Towards acceleration of fault simulation using graphics processing units. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
graphics processing units, fault simulation |
| 1 | Chunjie Duan, Chengyu Zhu, Sunil P. Khatri |
Forbidden transition free crosstalk avoidance CODEC design. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
crosstalk, CODEC, on-chip bus, Fibonacci number |
| 1 | Rajesh Garg, Charu Nagpal, Sunil P. Khatri |
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
single event upset (SEU), model, analysis |
| 1 | Sabyasachi Das, Sunil P. Khatri |
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sabyasachi Das, Sunil P. Khatri |
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Sabyasachi Das, Sunil P. Khatri |
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Charu Nagpal, Rajesh Garg, Sunil P. Khatri |
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Victor H. Cordero Calle, Sunil P. Khatri |
Clock Distribution Scheme using Coplanar Transmission Lines. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Gagandeep Mallarapu, Sunil P. Khatri |
A Single-supply True Voltage Level Shifter. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunjie Duan, Sunil P. Khatri |
Energy Efficient and High Speed On-Chip Ternary Bus. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Peng Li, Sunil P. Khatri |
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Sunil P. Khatri |
A novel, highly SEU tolerant digital circuit design approach. |
ICCD |
2008 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Jayakumar, Sunil P. Khatri |
A Predictably Low-Leakage ASIC Design Style. |
IEEE Trans. VLSI Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Vijay Nagarajan, Stefan Laendner, Nikhil Jayakumar, Olgica Milenkovic, Sunil P. Khatri |
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. |
VLSI Signal Processing |
2007 |
DBLP DOI BibTeX RDF |
code construction, fully-parallel VLSI implementation, network of PLAs, iterative decoding, low-density parity-check codes |
| 1 | Eugene Goldberg, Kanupriya Gulati, Sunil P. Khatri |
Toggle Equivalence Preserving (TEP) Logic Optimization. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Jeff L. Cobb, Rajesh Garg, Sunil P. Khatri |
A methodology for interconnect dimension determination. |
ISPD |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Jayakumar, Sunil P. Khatri |
An algorithm to minimize leakage through simultaneous input vector control and circuit modification. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
A Structured ASIC Design Approach Using Pass Transistor Logic. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
| 1 | Scott J. Campbell, Sunil P. Khatri |
Resource and delay efficient matrix multiplication using newer FPGA devices. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
FPGA, floating point, multiplier, matrix |
| 1 | Bo Shen, Sunil P. Khatri, Takis Zourntos |
Implementation of MOSFET based capacitors for digital applications. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
MOSFET capacitor, constant capacitance, reference capacitor |
| 1 | Rajesh Garg, Mario Sanchez, Kanupriya Gulati, Nikhil Jayakumar, Anshul Gupta, Sunil P. Khatri |
A design flow to optimize circuit delay by using standard cells and PLAs. |
ACM Great Lakes Symposium on VLSI |
2006 |
DBLP DOI BibTeX RDF |
PLA, standard cell |
| 1 | Nikhil Jayakumar, Rajesh Garg, Bruce Gamache, Sunil P. Khatri |
A PLA based asynchronous micropipelining approach for subthreshold circuit design. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
micro-pipelining, asynchronous, PLA, sub-threshold |
| 1 | Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan Choi |
A design approach for radiation-hard digital electronics. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
radiation-hard, SEU |
| 1 | Brock J. LaMeres, Kanupriya Gulati, Sunil P. Khatri |
Controlling inductive cross-talk and power in off-chip buses using CODECs. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Brock J. LaMeres, Sunil P. Khatri |
Bus stuttering: an encoding technique to reduce inductive noise in off-chip data transmission. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunjie Duan, Sunil P. Khatri |
Computing during supply voltage switching in DVS enabled real-time processors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Rajesh Garg, Sunil P. Khatri |
Generalized buffering of PTL logic stages using Boolean division. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Chunjie Duan, Kanupriya Gulati, Sunil P. Khatri |
Memory-based crosstalk canceling CODECs for on-chip buses. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
A probabilistic method to determine the minimum leakage vector for combinational designs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, M. Lovell, Sunil P. Khatri |
Efficient don't care computation for hierarchical designs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Jayakumar, Sunil P. Khatri, Kanupriya Gulati, Alexander Sprintson |
Network coding for routability improvement in VLSI. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
|
| 1 | Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil P. Khatri |
CMOS Comparators for High-Speed and Low-Power Applications. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri, Weiping Shi |
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri |
On the Improvement of Statistical Static Timing Analysis. |
ICCD |
2006 |
DBLP BibTeX RDF |
|
| 1 | Nikhil Saluja, Sunil P. Khatri |
Efficient SAT-based combinational ATPG using multi-level don't-cares. |
ITC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Kanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri |
An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designs. |
ISLPED |
2005 |
DBLP DOI BibTeX RDF |
BDD, leakage, ADD |
| 1 | Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri |
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
leakage power, self-adjusting, body-biasing |
| 1 | Nikhil Jayakumar, Sunil P. Khatri |
A variation tolerant subthreshold design approach. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
variation-toleran, self-adjusting, body-biasing, sub-threshold |
| 1 | Van R. Culver, Sunil P. Khatri |
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Edward Hursey, Nikhil Jayakumar, Sunil P. Khatri |
Non-Manhattan Routing Using a Manhattan Router. |
VLSI Design |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Brock J. LaMeres, Sunil P. Khatri |
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Brock J. LaMeres, Sunil P. Khatri |
Performance model for inter-chip communication considering inductive cross-talk and cost. |
ISCAS |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Ganesh Venkataraman, Nikhil Jayakumar, Jiang Hu, Peng Li, Sunil P. Khatri, Anand Rajaram, Patrick McGuinness, Charles J. Alpert |
Practical techniques to reduce skew and its variations in buffered clock networks. |
ICCAD |
2005 |
DBLP BibTeX RDF |
|
| 1 | Brock J. LaMeres, Sunil P. Khatri |
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Seraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra |
X-Routing using Two Manhattan Route Instances. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Nikhil Jayakumar, Sunil P. Khatri |
Minimum Energy Near-threshold Network of PLA based Design. |
ICCD |
2005 |
DBLP DOI BibTeX RDF |
|
| 1 | Sunil P. Khatri, Subarnarekha Sinha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli |
SPFD-based wire removal in standard-cell and network-of-PLA circuits. |
IEEE Trans. on CAD of Integrated Circuits and Systems |
2004 |
DBLP DOI BibTeX RDF |
|
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