Search results for "Superscalar Processors"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
4	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye	A technique to determine power-efficient, high-performance superscalar processors.	HICSS	1995	DBLP DOI BibTeX RDF	high-performance superscalar processors, processor performance advances, thermal power dissipation, architectural power estimates, systematic techniques, user benchmarks, architectural component, real estate usage, superscalar execution units, architectural power measurement, near-optimal search, power-efficient superscalar processors, performance evaluation, parallel architectures, simulated annealing, simulated annealing, parallel machines, power consumption, trace-driven simulation
3	Patrick Ndai, Swarup Bhunia, Amit Agarwal, Kaushik Roy	Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Variable-cycle functional unit, speed binning, Scheduling, process variation, Superscalar Processors
3	Pierre Michaud, André Seznec, Stéphan Jourdan	Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors.	IEEE PACT	1999	DBLP DOI BibTeX RDF	instruction-level parallelism, branch prediction, superscalar processors, instruction fetch
3	Chris Stolte, Robert Bosch, Pat Hanrahan, Mendel Rosenblum	Visualizing Application Behavior on Superscalar Processors.	INFOVIS	1999	DBLP DOI BibTeX RDF	Computer systems visualization, superscalar processors, visualization systems
3	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
3	Marc Tremblay, Bill Joy, Ken Shin	A three dimensional register file for superscalar processors.	HICSS	1995	DBLP DOI BibTeX RDF	three dimensional register file, datapath component, three-scalar machine, 3D Register File, multiple planes, extra register sets, microtask switching, data array, ported register file, flat register file, bus lines, large buffer, simulations, performance evaluation, data structures, memory architecture, superscalar processors, file organisation, registers, access time, microcomputers, cycle time, real time tasks, superscalar microprocessor, superscalar microprocessors, register windows
2	Omer Khan, Sandip Kundu	A model to exploit power-performance efficiency in superscalar processors via structure resizing.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	modeling, power
2	Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras	Interval-based models for run-time DVFS orchestration in superscalar processors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
2	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
2	Stijn Eyerman, Lieven Eeckhout, James E. Smith	Studying Compiler Optimizations on Superscalar Processors Through Interval Analysis.	HiPEAC	2008	DBLP DOI BibTeX RDF
2	Tejas Karkhanis, James E. Smith	Automated design of application specific superscalar processors: an analytical approach.	ISCA	2007	DBLP DOI BibTeX RDF	performance model, analytical model, design optimization, energy model, application specific processors
2	Mojtaba Shakeri, Abolfazl Toroghi Haghighat, Mohammad K. Akbari	Modeling and Evaluating the Scalability of Instruction Fetching in Superscalar Processors.	ITNG	2007	DBLP DOI BibTeX RDF
2	Kuo-Su Hsiao, Chung-Ho Chen	An efficient wakeup design for energy reduction in high-performance superscalar processors.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	issue window, wakeup logic, low power, high performance
2	Ingomar Wenzel, Raimund Kirner, Peter P. Puschner, Bernhard Rieder	Principles of Timing Anomalies in Superscalar Processors.	QSIC	2005	DBLP DOI BibTeX RDF
2	Oliverio J. Santana, Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero	A low-complexity fetch architecture for high-performance superscalar processors.	TACO	2004	DBLP DOI BibTeX RDF	fetch architecture, instruction stream, high performance, Branch prediction, low complexity
2	Amir Rajabzadeh, Seyed Ghassem Miremadi, Mirzad Mohandespour	Error Detection Enhancement in COTS Superscalar Processors with Performance Monitoring Features.	J. Electronic Testing	2004	DBLP DOI BibTeX RDF	COTS processors, fault injection, performance monitoring, analytical evaluation, watchdog processor, error detection coverage
2	Amir Rajabzadeh, Mirzad Mohandespour, Seyed Ghassem Miremadi	Error Detection Enhancement in COTS Superscalar Processors with Event Monitoring Features.	PRDC	2004	DBLP DOI BibTeX RDF
2	Aneesh Aggarwal	Single FU Bypass Networks for High Clock Rate Superscalar Processors.	HiPC	2004	DBLP DOI BibTeX RDF
2	Marc Epalza, Paolo Ienne, Daniel Mlynek	Adding Limited Reconfigurability to Superscalar Processors.	IEEE PACT	2004	DBLP DOI BibTeX RDF
2	Muhammad Shaaban, Edward Mulrane	Improving trace cache hit rates using the sliding window fill mechanism and fill select table.	Memory System Performance	2004	DBLP DOI BibTeX RDF	branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache
2	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
2	Santithorn Bunchua, D. Scott Wills, Linda M. Wills	Reducing Operand Transport Complexity of Superscalar Processors using Distributed Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
2	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
2	André Seznec, Eric Toullec, Olivier Rochecouste	Register write specialization register read specialization: a path to complexity-effective wide-issue superscalar processors.	MICRO	2002	DBLP DOI BibTeX RDF
2	Seongwoo Kim, Arun K. Somani	SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors.	PRDC	2001	DBLP DOI BibTeX RDF
2	Sébastien Nussbaum, James E. Smith	Modeling Superscalar Processors via Statistical Simulation.	IEEE PACT	2001	DBLP DOI BibTeX RDF
2	Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi	Reducing the complexity of the register file in dynamic superscalar processors.	MICRO	2001	DBLP DOI BibTeX RDF
2	Jorge E. Carrillo, Paul Chow	The effect of reconfigurable units in superscalar processors.	FPGA	2001	DBLP DOI BibTeX RDF	OneChip, superscalar processors, reconfigurable processors
2	Jian Huang, David J. Lilja	Exploring Sub-Block Value Reuse for Superscalar Processors.	IEEE PACT	2000	DBLP DOI BibTeX RDF
2	Simonjit Dutta, Manoj Franklin	Control Flow Prediction Schemes for Wide-Issue Superscalar Processors.	IEEE Trans. Parallel Distrib. Syst.	1999	DBLP DOI BibTeX RDF	Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP)
2	Srivatsan Srinivasan, Lizy Kurian John	On the Use of Pseudorandom Sequences for High Speed Resource Allocators in Superscalar Processors.	ICCD	1999	DBLP DOI BibTeX RDF	hardware resource allocation, superscalar processor, pseudorandom sequences, reorder buffer
2	Jörn Schneider, Christian Ferdinand	Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation.	Workshop on Languages, Compilers, and Tools for Embedded Systems	1999	DBLP DOI BibTeX RDF
2	Eric Rotenberg, Steve Bennett, James E. Smith	A Trace Cache Microarchitecture and Evaluation.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching
2	James J. Carrig Jr., Gerard G. L. Meyer	Efficient Householder QR Factorization for Superscalar Processors.	ACM Trans. Math. Softw.	1997	DBLP DOI BibTeX RDF	Householder QR factorization, register model, cache model
2	Soohong P. Kim, Raymond Hoare, Henry G. Dietz	VLIW Across Multiple Superscalar Processors on a Single Chip.	IEEE PACT	1997	DBLP DOI BibTeX RDF
2	Michael J. Flynn	What's ahead in computer design?	EUROMICRO	1997	DBLP DOI BibTeX RDF	die area improvement, very high level superscalar processors, very large cache, pin bandwidth, processor complexity, scalability, multiprocessors, logic design, instruction level parallelism, VLIW, CMOS technology, lithography, cycle time, computer design, silicon area, cache size
2	Meng-chou Chang, Feipei Lai	Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	multilevel boosting, shadow register file, conjugate register file, scheduling-conflict graph, Instruction-level parallelism, speculative execution, superscalar processors
2	Bernard Goossens, Duc Thang Vu	Multithreading to Improve Cycle Width and CPI in Superpipelined Superscalar Processors.	ISPAN	1996	DBLP DOI BibTeX RDF	Superpipelined Processors, Architecture, Instruction Level Parallelism, Superscalar Processors, Multithreaded Processors
2	Eric Rotenberg, Steve Bennett, James E. Smith	Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching.	MICRO	1996	DBLP BibTeX RDF	multiple branch prediction, superscalar processors, instruction cache, trace cache, instruction fetching
2	Roger Collins, Gordon Steven	Instruction Scheduling for a Superscalar Architecture.	EUROMICRO	1996	DBLP DOI BibTeX RDF	compile-time instruction scheduling, conditional group scheduler, HSA processor model, guarded instruction execution, instruction squashing, instruction buffer, performance evaluation, superscalar processors, superscalar architecture, functional units, branch instructions
2	Eliseu M. Chaves Filho, Edil S. Tavares Fernandes, Andrew Wolfe	Load Balancing in Superscalar Architectures.	EUROMICRO	1996	DBLP DOI BibTeX RDF	multiple functional units, parallel instruction execution, processor throughput, dynamic instruction-issuing algorithm, performance, load balancing, parallel architectures, instruction-level parallelism, superscalar processors, application program, computational load, superscalar architectures, hardware resources
2	Ching-Long Su, Alvin M. Despain	Cache designs for energy efficiency.	HICSS	1995	DBLP DOI BibTeX RDF	cache design techniques, superpipelined processors, cache energy consumption estimation, block buffering, cache sub-banking, Gray code addressing, instruction cache designs, consecutive accessing, energy efficiency, microprocessors, power consumption, energy conservation, data caches, cache storage, superscalar processors, Gray codes, energy reduction, CMOS memory circuits
2	Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ACM Trans. Comput. Syst.	1993	DBLP DOI BibTeX RDF	exception detection, exception recovery, instruction-level parallelism, instruction scheduling, speculative execution, superscalar processor, VlIW processor
2	Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker	Sentinel Scheduling for VLIW and Superscalar Processors.	ASPLOS	1992	DBLP DOI BibTeX RDF
1	Brandon H. Dwiel, Niket Kumar Choudhary, Eric Rotenberg	FPGA modeling of diverse superscalar processors.	ISPASS	2012	DBLP DOI BibTeX RDF
1	Osman Allam, Stijn Eyerman, Lieven Eeckhout	An efficient CPI stack counter architecture for superscalar processors.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
1	Jongmyon Kim, Linda M. Wills, D. Scott Wills	Color-Aware Instructions for Embedded Superscalar Processors.	Signal Processing Systems	2011	DBLP DOI BibTeX RDF
1	Wen-mei Hwu	Superscalar Processors.	Encyclopedia of Parallel Computing	2011	DBLP DOI BibTeX RDF
1	Muawya Al-Otoom, Elliott Forbes, Eric Rotenberg	EXACT: explicit dynamic-branch prediction with active updates.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	branch prediction, microarchitecture, superscalar processors
1	Jih-Ching Chiu, Yu-Liang Chou, Ding-Siang Su	A hyperscalar multi-core architecture.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	cmps, dynamic multi-core chips, reconfigurable multi-core architectures, chip multiprocessors
1	Elham Safi, Andreas Moshovos, Andreas G. Veneris	A physical-level study of the compacted matrix instruction scheduler for dynamically-scheduled superscalar processors.	ICSAMOS	2009	DBLP DOI BibTeX RDF
1	Nasir Mohyuddin, Kimish Patel, Massoud Pedram	Deterministic clock gating to eliminate wasteful activity due to wrong-path instructions in out-of-order superscalar processors.	ICCD	2009	DBLP DOI BibTeX RDF
1	Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González, Oguz Ergin	Exploring the limits of early register release: Exploiting compiler analysis.	TACO	2009	DBLP DOI BibTeX RDF	compiler, energy efficiency, Low-power design, microarchitecture, register file
1	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A mechanistic performance model for superscalar out-of-order processors.	ACM Trans. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Superscalar out-of-order processor, balanced processor design, mechanistic modeling, overprovisioned processor design, pipeline depth, pipeline width, resource scaling, wide front-end dispatch processors, performance modeling, analytical modeling
1	Kiyeon Lee, Shayne Evans, Sangyeun Cho	Accurately approximating superscalar processor performance from traces.	ISPASS	2009	DBLP DOI BibTeX RDF
1	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
1	Aneesh Aggarwal	Complexity Effective Bypass Networks.	T. HiPEAC	2009	DBLP DOI BibTeX RDF
1	Zhao Xianfeng	Structural Optimization on Superscalar Processors.	CSSE	2008	DBLP DOI BibTeX RDF
1	Frederico Pratas, Georgi Gaydadjiev, Mladen Berekovic, Leonel Sousa, Stefanos Kaxiras	Low power microarchitecture with instruction reuse.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	loop reusing technique, reorder buffer optimization, superscalar processor, power reduction
1	Yi-Ying Tsai, Chia-Jung Hsu, Chung-Ho Chen	Address compression for scalable load/store queue implementation.	ISCAS	2008	DBLP DOI BibTeX RDF
1	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Power Reduction of Functional Units Considering Temperature and Process Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
1	Noel Tomás, Julio Sahuquillo, Salvador Petit, Pedro López	Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot.	Euro-Par	2008	DBLP DOI BibTeX RDF
1	Tameesh Suri	Improving instruction level parallelism through reconfigurable units in superscalar processors.	SIGARCH Computer Architecture News	2007	DBLP DOI BibTeX RDF
1	Sven van Haastregt, Peter M. W. Knijnenburg	Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search.	DATE	2007	DBLP DOI BibTeX RDF
1	Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat	By-passing the out-of-order execution pipeline to increase energy-efficiency.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	instruction wake-up, energy-efficiency, instruction scheduling, out-of-order execution
1	Simha Sethumadhavan, Franziska Roesner, Joel S. Emer, Doug Burger, Stephen W. Keckler	Late-binding: enabling unordered load-store queues.	ISCA	2007	DBLP DOI BibTeX RDF	network flow control, memory disambiguation, late binding
1	Ernie Chan, Enrique S. Quintana-Ortí, Gregorio Quintana-Ortí, Robert A. van de Geijn	Supermatrix out-of-order scheduling of matrix operations for SMP and multi-core architectures.	SPAA	2007	DBLP DOI BibTeX RDF	data affinity, data-flow parallelism, dense linear algebra libraries, dynamic scheduling, out-of-order execution
1	Ruchira Sasanka, Man-Lap Li, Sarita V. Adve, Yen-Kuang Chen, Eric Debes	ALP: Efficient support for all levels of parallelism for complex media applications.	TACO	2007	DBLP DOI BibTeX RDF	media applications, multimedia, Parallelism, SIMD, vector, TLP, DLP, data-level parallelism
1	Viswanathan Subramanian, Mikel Bezdek, Naga Durga Prasad Avirneni, Arun K. Somani	Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning.	DSN	2007	DBLP DOI BibTeX RDF	overclocking, Reliability, Fault-Tolerant Computing, Dynamic, Superscalar processor
1	Rajesh Vivekanandham, R. Govindarajan	A Scalable Low Power Store Queue for Large InstructionWindow Processors.	PACT	2007	DBLP DOI BibTeX RDF
1	Stijn Eyerman, Lieven Eeckhout, Tejas Karkhanis, James E. Smith	A Top-Down Approach to Architecting CPI Component Performance Counters.	IEEE Micro	2007	DBLP DOI BibTeX RDF	hardware performance counter architecture, superscalar processor performance modeling, performance, measurement, experimentation, modeling techniques
1	Yongfeng Pan, Xiaoya Fan, Liqiang He, Deli Wang	A Bypass Mechanism to Enhance Branch Predictor for SMT Processors.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
1	Neal A. Harman	Algebraic Models of Simultaneous Multithreaded and Multi-core Processors.	CALCO	2007	DBLP DOI BibTeX RDF	many-sorted algebra, verification, microprocessors, correctness, threaded
1	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	International Journal of Parallel Programming	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
1	José R. Herrero, Juan J. Navarro	Exploiting computer resources for fast nearest neighbor classification.	Pattern Anal. Appl.	2007	DBLP DOI BibTeX RDF
1	Juan L. Aragón, José M. González, Antonio González	Control Speculation for Energy-Efficient Next-Generation Superscalar Processors.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	low-power design, processor architecture, energy-aware systems, Control speculation
1	P. J. Joseph, Kapil Vaswani, Matthew J. Thazhuthaveetil	A Predictive Performance Model for Superscalar Processors.	MICRO	2006	DBLP DOI BibTeX RDF
1	Houman Homayoun, Ted H. Szymanski	Reducing the Instruction Queue Leakage Power in Superscalar Processors.	CCECE	2006	DBLP DOI BibTeX RDF
1	Junwei Zhou, Andrew Mason	A two-level hybrid select logic for wide-issue superscalar processors.	ISCAS	2006	DBLP DOI BibTeX RDF
1	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
1	Rajesh Vivekanandham, Bharadwaj S. Amrutur, R. Govindarajan	A scalable low power issue queue for large instruction window processors.	ICS	2006	DBLP DOI BibTeX RDF	complexity-effective architecture, wakeup logic, low-power architecture, issue logic
1	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
1	Hui Zeng, Kanad Ghose	Register file caching for energy efficiency.	ISLPED	2006	DBLP DOI BibTeX RDF	register caching, energy-efficiency, register files
1	Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau	CAVA: Using checkpoint-assisted value prediction to hide L2 misses.	TACO	2006	DBLP DOI BibTeX RDF	checkpointed processor architectures, multiprocessor, memory hierarchies, Value prediction
1	Olivier Rochecouste, Gilles Pokam, André Seznec	A case for a complexity-effective, width-partitioned microarchitecture.	TACO	2006	DBLP DOI BibTeX RDF	Power analysis
1	Gihan R. Mudalige, Stephen A. Jarvis, Daniel P. Spooner, Graham R. Nudd	Predictive Performance Analysis of a Parallel Pipelined Synchronous Wavefront Application for Commodity Processor Cluster Systems.	CLUSTER	2006	DBLP DOI BibTeX RDF
1	Samantika Subramaniam, Gabriel H. Loh	Store vectors for scalable memory dependence prediction and scheduling.	HPCA	2006	DBLP DOI BibTeX RDF
1	Anne Bracy, Amir Roth	Serialization-Aware Mini-Graphs: Performance with Fewer Resources.	MICRO	2006	DBLP DOI BibTeX RDF
1	Jonathan Barre, Cédric Landet, Christine Rochange, Pascal Sainrat	Modeling Instruction-Level Parallelism for WCET Evaluation.	RTCSA	2006	DBLP DOI BibTeX RDF
1	Maurício L. Pilla, Bruce R. Childers, Amarildo T. da Costa, Felipe M. G. França, Philippe Olivier Alexandre Navaux	A Speculative Trace Reuse Architecture with Reduced Hardware Requirements.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
1	Jaeheon Jeong, Michel Dubois	Cache Replacement Algorithms with Nonuniform Miss Costs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Cache, power, latency, trace-driven simulations, memory system, replacement policy
1	Stefan Tillich, Johann Großschädl	Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors.	CHES	2006	DBLP DOI BibTeX RDF	embedded RISC processor, SPARC V8 architecture, Advanced Encryption Standard, instruction set extensions, efficient implementation
1	Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew	Supporting Speculative Multithreading on Simultaneous Multithreaded Processors.	HiPC	2006	DBLP DOI BibTeX RDF
1	Oleg Bessonov, Dominique Fougère, Bernard Roux	Development of efficient computational kernels and linear algebra routines for out-of-order superscalar processors.	Future Generation Comp. Syst.	2005	DBLP DOI BibTeX RDF
1	Julio Sahuquillo, Salvador Petit, Ana Pont, Veljko M. Milutinovic	Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors.	Journal of Systems Architecture	2005	DBLP DOI BibTeX RDF
1	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
1	Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara	Testing Superscalar Processors in Functional Mode.	FPL	2005	DBLP BibTeX RDF
1	Pierre Salverda, Craig B. Zilles	A Criticality Analysis of Clustering in Superscalar Processors.	MICRO	2005	DBLP DOI BibTeX RDF
1	Peng Zhou, Soner Önder, Steve Carr	Fast branch misprediction recovery in out-of-order superscalar processors.	ICS	2005	DBLP DOI BibTeX RDF	processor state, checkpoint, recovery, branch misprediction
1	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors