Search results for "Supply gating"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
3	Swarup Bhunia, Hamid Mahmoodi, Arijit Raychowdhury, Kaushik Roy	Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique.	J. Electronic Testing	2008	DBLP DOI BibTeX RDF	Enhanced scan, Supply gating, Delay fault testing, Two-pattern testing
2	Lawrence Leinweber, Swarup Bhunia	Fine-Grained Supply Gating Through Hypergraph Partitioning and Shannon Decomposition for Active Power Reduction.	DATE	2008	DBLP DOI BibTeX RDF
2	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Low-Power and testable circuit synthesis using Shannon decomposition.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	Shannon expansion, dynamic supply gating, test coverage, Design-for-test, IDDQ, noise immunity, test power
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy	Low-power scan design using first-level supply gating.	IEEE Trans. VLSI Syst.	2005	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Kaushik Roy	Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.	ISQED	2005	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy	A novel synthesis approach for active leakage power reduction using dynamic supply gating.	DAC	2005	DBLP DOI BibTeX RDF
2	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy	A Novel Low-Power Scan Design Technique Using Supply Gating.	ICCD	2004	DBLP DOI BibTeX RDF
1	Lei Wang, Somnath Paul, Swarup Bhunia	Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory.	VLSI Design	2012	DBLP DOI BibTeX RDF
1	Somnath Paul, Swarup Bhunia	VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement.	ISLPED	2010	DBLP DOI BibTeX RDF	narrow-width operand, superscalar processor, within-die variation
1	Mesut Meterelliyoz, Kaushik Roy	Design for burn-in test: a technique for burn-in thermal stability under die-to-die parameter variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Arijit Raychowdhury, Kaushik Roy, Swarup Bhunia, Hamid Mahmoodi	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	IEEE Trans. VLSI Syst.	2006	DBLP DOI BibTeX RDF
1	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy	Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.	DATE	2005	DBLP DOI BibTeX RDF
1	Nilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy	Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.	ICCD	2005	DBLP DOI BibTeX RDF
1	Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	Reducing leakage energy in FPGAs using region-constrained placement.	FPGA	2004	DBLP DOI BibTeX RDF	region-constrained placement, FPGA, leakage power
1	Swarup Bhunia, Hamid Mahmoodi-Meimand, Arijit Raychowdhury, Kaushik Roy	First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.	DFT	2004	DBLP DOI BibTeX RDF
1	Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Characterization and modeling of run-time techniques for leakage power reduction.	IEEE Trans. VLSI Syst.	2004	DBLP DOI BibTeX RDF
1	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
1	Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin	Implications of technology scaling on leakage reduction techniques.	DAC	2003	DBLP DOI BibTeX RDF	low power, technology scaling, leakage reduction
1	David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin	Evaluating Run-Time Techniques for Leakage Power Reduction.	VLSI Design	2002	DBLP DOI BibTeX RDF