Search results for "Supratik Chakraborty"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Bhargav S. Gulavani, Supratik Chakraborty, G. Ramalingam, Aditya V. Nori	Bottom-up shape analysis using LISF.	ACM Trans. Program. Lang. Syst.	2011	DBLP DOI BibTeX RDF
1	Hrishikesh Karmarkar, Supratik Chakraborty	Determinization of $\omega$-automata unified	CoRR	2011	DBLP BibTeX RDF
1	Ajith K. John, Supratik Chakraborty	A Quantifier Elimination Algorithm for Linear Modular Equations and Disequations.	CAV	2011	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Amit Kumar	Frontmatter, Table of Contents, Preface, Conference Organization, External Reviewers.	FSTTCS	2011	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Amit Kumar (eds.)	IARCS Annual Conference on Foundations of Software Technology and Theoretical Computer Science, FSTTCS 2011, December 12-14, 2011, Mumbai, India	FSTTCS	2011	DBLP BibTeX RDF
1	Bhargav S. Gulavani, Supratik Chakraborty, Aditya V. Nori, Sriram K. Rajamani	Refining abstract interpretations.	Inf. Process. Lett.	2010	DBLP DOI BibTeX RDF
1	Abhisekh Sankaran, Supratik Chakraborty	On Semantic Generalizations of the Bernays-Schönfinkel-Ramsey Class with Finite or Co-finite Spectra	CoRR	2010	DBLP BibTeX RDF
1	Jeff Edmonds, Supratik Chakraborty	Bounding Variance and Expectation of Longest Path Lengths in DAGs.	SODA	2010	DBLP BibTeX RDF
1	Hrishikesh Karmarkar, Supratik Chakraborty	On Minimal Odd Rankings for Büchi Complementation.	ATVA	2009	DBLP DOI BibTeX RDF
1	Bhargav S. Gulavani, Supratik Chakraborty, Ganesan Ramalingam, Aditya V. Nori	Bottom-Up Shape Analysis.	SAS	2009	DBLP DOI BibTeX RDF
1	Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya	Efficient guided symbolic reachability using reachability expressions.	STTT	2008	DBLP DOI BibTeX RDF
1	Bhargav S. Gulavani, Supratik Chakraborty, Aditya V. Nori, Sriram K. Rajamani	Automatically Refining Abstract Interpretations.	TACAS	2008	DBLP DOI BibTeX RDF
1	Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil	A Scalable Symbolic Simulator for Verilog RTL.	MTV	2007	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Joycee Mekie, Dinesh K. Sharma	Reasoning about synchronization in GALS systems.	Formal Methods in System Design	2006	DBLP DOI BibTeX RDF	Symbolic timing analysis, GALS systems, Multi-clocked systems, Symbolic delay constraints, Synchronization constraints, Sequencing constraints
1	Dina Thomas, Supratik Chakraborty, Paritosh K. Pandya	Efficient Guided Symbolic Reachability Using Reachability Expressions.	TACAS	2006	DBLP DOI BibTeX RDF
1	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma, Girish Venkataramani, P. S. Thiagarajan	Interface Design for Rationally Clocked GALS Systems.	ASYNC	2006	DBLP DOI BibTeX RDF
1	Babita Sharma, Paritosh K. Pandya, Supratik Chakraborty	Bounded Validity Checking of Interval Duration Logic.	TACAS	2005	DBLP DOI BibTeX RDF
1	Joycee Mekie, Supratik Chakraborty, Dinesh K. Sharma	Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework.	VLSI Design	2004	DBLP DOI BibTeX RDF
1	Rohan Angrish, Supratik Chakraborty	Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay.	ASYNC	2002	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Rajeev Murgai	Layout-Driven Timing Optimization by Generalized De Morgan Transform.	VLSI Design	2002	DBLP DOI BibTeX RDF	layout-driven optimization, in-place circuit optimization, DeMorgan transformation, deep sub-micron design, Timing optimization, timing closure
1	Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan	Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract).	VLSI Design	2002	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Rajeev Murgai	Complexity Of Minimum-Delay Gate Resizing.	VLSI Design	2001	DBLP DOI BibTeX RDF
1	Kenneth Y. Yun, Kevin W. James, R. H. Fairlie-Cuninghame, Supratik Chakraborty, Rene L. Cruz	A self-timed real-time sorting network.	IEEE Trans. VLSI Syst.	2000	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, Kenneth Y. Yun, David L. Dill	Timing analysis of asynchronous systems using time separation of events.	IEEE Trans. on CAD of Integrated Circuits and Systems	1999	DBLP DOI BibTeX RDF
1	Supratik Chakraborty, David L. Dill, Kun-Yung Chang, Kenneth Y. Yun	Timing Analysis of Extended Burst-Mode Circuits.	ASYNC	1997	DBLP DOI BibTeX RDF	Extended burst-mode circuits, 3D design style, global timing constraints, uncertain component delays, thirteen-valued signal algebra, polynomial-time
1	Supratik Chakraborty, David L. Dill	More Accurate Polynomial-Time Min-Max Timing Simulation.	ASYNC	1997	DBLP DOI BibTeX RDF	Uncertain component delays, min-max timing simulation, thirteen-valued signal algebra, polynomial-time algorithm
1	Supratik Chakraborty, David L. Dill	Approximate algorithms for time separation of events.	ICCAD	1997	DBLP DOI BibTeX RDF	Time separation of events, timing constraint graph, min/max constraints, conservative approximation, non-convex feasible space, convex approximation, polynomial-time algorithm
1	Supratik Chakraborty, Dipanwita Roy Chowdhury, Parimal Pal Chaudhuri	Theory and Application of Nongroup Cellular Automata for Synthesis of Easily Testable Finite State Machines.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	synthesis for testability (SFT), testable sequential machines, Cellular automata
1	S. Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy	Delay Fault Test Generation with Cellular Automata.	VLSI Design	1993	DBLP BibTeX RDF
1	Dipanwita Roy Chowdhury, Supratik Chakraborty, Parimal Pal Chaudhuri	Synthesis of Self-Checking Sequential Machines Using Cellular Automata.	VLSI Design	1993	DBLP BibTeX RDF
1	Dipanwita Roy Chowdhury, Supratik Chakraborty, B. Vamsi, B. Pal Chaudhuri	Cellular automata based synthesis of easily and fully testable FSMs.	ICCAD	1993	DBLP DOI BibTeX RDF

Publications of "Supratik Chakraborty" ( http://dblp.L3S.de/Authors/Supratik_Chakraborty )